AK5366VR Datasheet, PDF (12/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
Parameter
Symbol
min
typ
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
(Note 21) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
CSN “↑” to SDTO valid
(Note 22) tPD
150
(Note 23) tPDV
516
(Note 24) tPDV
516
Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 22. The AK5366VR can be reset by bringing the PDN pin = “L”.
Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Note 24. This cycle is the number of LRCK rising edges from the CSN = “H”.
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
400
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
0.3
µs
0.3
µs
-
µs
50
ns
ns
1/fs
1/fs
Purchase of Asahi Kasei Microsystems Co., Ltd I²C components conveys a license under the Philips
I²C patent to use the components in the I²C system, provided the system conform to the I²C
specifications defined by Philips.
MS0526-E-00
- 12 -
2006/07