AK5366VR Datasheet, PDF (17/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
[MCLK AC Coupling input]
MCLK AC coupling input becomes possible by controlling MCKPD bit and MCKAC bit.
Master Clock
Status
MCKAC bit
External Clock Direct Input (Figure 1) Clock is input to MCLK pin.
0
Clock isn’t input to MCLK pin.
0
AC Coupling Input
(Figure 2) Clock is input to MCLK pin.
1
Clock isn’t input to MCLK pin.
1
Table 3. MCKPD bit and MCKAC bit setting for Master Clock Status
MCKPD bit
0
Don’t care
0
1
(1) External clock direct input
MCLK
External
Clock
MCKAC = "0"
MCKPD = "0"
AK5366VR
(2) AC coupling input
Figure 1. External Master Clock Input Block
C _MCLK
External
Clock
MCKAC = "1"
MCKPD = "0"
AK5366VR
Figure 2. External Clock mode (Input : ≥ 50%DVDD, Input circuit example)
- Note: This clock level must not exceed DVDD level. (C : 0.1µF)
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF bit (Table 4). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and
slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF bit
0
1
SDTO
LRCK
BICK
24bit, MSB justified
H/L
≥ 48fs (Slave)
64fs (Master)
24bit, I²S Compatible
L/H
≥ 48fs (Slave)
64fs (Master)
Table 4. Audio Interface Format
Figure
Figure 3 Default
Figure 4
MS0526-E-00
- 17 -
2006/07