AK5366VR Datasheet, PDF (19/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
„ Power-up/down
The AK5366VR is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the
same time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the
power-down mode. Therefore, the output data SDTO becomes available after 516 cycles of LRCK.
Power Supply
PDN pin
150ns
ADC Internal State
PDN
INITA
Normal
ALC bit
“1”
“0”
ALC Function
ON
OFF
IPGA
Unknown
(1)
SDTO
External clocks
in slave mode
External clocks
in master mode
BICK, LRCK
in master mode
“0”
Output
MCLK, BICK, LRCK Input
The clocks can be stopped.
MCLK Input
Fixed to “L”
BICK, LRCK Output
• PDN : Power down state.
• INITA : Initializing period of ADC analog section (516/fs).
• (1) : After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation.
Figure 5. Power-up Sequence
„ Peak Hold Circuit
The AK5366VR includes the peak hold circuit. The peak is held L/R audio data independently. These registers are reset
by reading 8bit of MSB, reading 8bit of both MSB and LSB should be continuity controlled by reading in order of 8bit of
MSB from LSB. After reading 8bit of LSB the last, 8bit of MSB is lost by reading 8bit of LSB the last. The output value
is the absolute value. Full scale is “FFFFH”.
MS0526-E-00
- 19 -
2006/07