AK5366VR Datasheet, PDF (38/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
Addr
07H
Register Name
ALC Mode Control 2
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
0
D5
REF5
R/W
0
D4
REF4
R/W
0
D3
REF3
R/W
1
D2
REF2
R/W
1
D1
REF1
R/W
1
D0
REF0
R/W
0
REF7-0: Reference value at ALC recovery operation (see Table 21)
During the ALC recovery operation, if the IPGA value exceeds the setting reference value by gain operation,
then the IPGA does not become larger than the reference value.
The REF7-0 bits should not be set up except for Table 21.
DATA (hex) Gain (dB)
A4H
+18.0
:
:
90H
+8.0
8FH
+7.5
8EH
+7.0
Default
8DH
+6.5
:
:
89H
+4.5
:
:
81H
+0.5
80H
0
Table 21. Reference value at ALC recovery operation
Addr
08H
09H
Register Name
Lch DATT Control
Rch DATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
1
D5
ATTL5
ATTR5
R/W
1
D4
ATTL4
ATTR4
R/W
1
D3
ATTL3
ATTR3
R/W
1
D2
ATTL2
ATTR2
R/W
1
D1
ATTL1
ATTR1
R/W
1
D0
ATTL0
ATTR0
R/W
1
ATTL/R7-0: Digital output volume control (see Table 11)
Initial value is “7FH”.
The data must not be written over 90H.
When PDN pin = “L”, ATTL/R7-0 bits are initialized “7FH”.
When PWN bit = “0”, the DATT holds the last setting value.
Addr
0AH
0BH
0CH
0DH
Register Name
Lch Peak Hold Low Byte
Lch Peak Hold High Byte
Rch Peak Hold Low Byte
Rch Peak Hold High Byte
R/W
Default
D7
PHL7
PHL15
PHR7
PHR15
0
D6
PHL6
PHL14
PHR6
PHR14
0
D5
PHL5
PHL13
PHR5
PHR13
0
D4
D3
PHL4 PHL3
PHL12 PHL11
PHR4 PHR3
PHR12 PHR11
RD
0
0
D2
PHL2
PHL10
PHR2
PHR10
0
D1
PHL1
PHL9
PHR1
PHR9
0
D0
PHL0
PHL8
PHR0
PHR8
0
PHL15-0: Lch Peak Hold Low/High Byte
PHR15-0: Rch Peak Hold Low/High Byte
The AK5366VR includes the peak hold circuit. The peak is held L/R audio data independently. These
registers are reset by reading 8bit of MSB, reading 8bit of both MSB and LSB should be continuity
controlled by reading in order of 8bit of MSB from LSB. After reading 8bit of LSB the last, 8bit of MSB
is lost by reading 8bit of LSB the last. The output value is the absolute value. Full scale is “FFFFH”.
These registers are reset by PDN pin = “L” or PWN bit = “0”.
MS0526-E-00
- 38 -
2006/07