AK5366VR Datasheet, PDF (34/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
„ Register Definitions
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Power Down & Reset Control 0
0
0
0
0
MCKPD MCKAC PWN
R/W
RD
RD
RD
RD
RD
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
PWN:
Power down control
0 : Power down. All registers are not initialized.
1 : Normal Operation (Default)
“0” powers down all sections and then both IPGA and ADC do not operate. The contents of all register
are not initialized and enabled to write to the registers.
When MCLK and LRCK are changed, it is not necessary to reset by the PDN pin or PWN bit because the
AK5366VR builds in reset-free circuit. However, it can be reduced the noise by reset.
MCKAC: Master Clock input Mode Select
0 : CMOS input (Default)
1 : AC coupling input
MCKPD: MCLK Input Buffer Control
0 : Enable (Default)
1 : Disable
When MCLK input with AC coupling is stopped, MCKPD bit should be set to “1”.
Addr
01H
Register Name
Input Selector Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
SEL2 SEL1 SEL0
RD
RD
RD
RD
RD
R/W
R/W
R/W
0
0
0
0
0
0
0
0
SEL2-0:
Input selector (see Table 6)
Initial values are “000”.
Addr
02H
Register Name
Clock & Format Control
R/W
Default
D7
D6
D5
0
0
0
RD
RD
RD
0
0
0
SMUTE: Soft Mute control
0 : Normal Operation (Default)
1 : SDTO outputs soft-muted.
CKS1-0: Master clock frequency select (see Table 2)
Initial values are “00”.
DIF: Audio interface format (see Table 4)
Initial values are “0” (24bit, MSB first).
D4
D3
D2
D1
D0
0
DIF
CKS1 CKS0 SMUTE
RD
R/W
R/W
R/W
R/W
0
0
0
0
0
MS0526-E-00
- 34 -
2006/07