AK5366VR Datasheet, PDF (30/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
(2) I²C-bus Control Mode (CTRL pin = “H”)
The AK5366VR supports the standard-mode and the first-mode I²C-bus system (max: 400kHz).
(2)-1. WRITE Operations
Figure 16 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 22). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next one bit are CAD1 (device
address bits). This one bit identify the specific device on the bus. The hard-wired input pin (CAD1 pin) set these device
address bits (Figure 17). If the slave address matches that of the AK5366VR, the AK5366VR generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 23). A R/W bit value of “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5366VR. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 18). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 19). The AK5366VR generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 22).
The AK5366VR can perform more than one byte write operation per sequence. After receipt of the third byte the
AK5366VR generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit
address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 0DH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 24) except for the START and STOP
conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 16. Data Transfer Sequence at the I²C-Bus Mode
0
0
1
0
0 CAD1 1
R/W
(CAD1 should match with CAD1 pin.)
Figure 17. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 18. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 19. Byte Structure after the second byte
MS0526-E-00
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2006/07