AK5366VR Datasheet, PDF (27/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
[4] Example of ALC Operation
The following registers should not be changed during the ALC operation.
• LTM1-0, LMTH, LMAT, WTM1-0, ZTM1-0, RATT, REF7-0, ZELMN bits
• The IPGA value of Lch becomes the start value if the IPGA value is different with Lch and Rch when the ALC starts.
• Writing to the area over 80H (Table 17) of IPGL/R registers (04H, 05H) is ignored during ALC operation.
After ALC is disabled, the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to
the
DATT area (Table 11) of DATT registers (08H, 09H), the DATT changes even if ALC is enabled.
PDN = “L” → “H”
ALC Operation
ALC OFF (WR: ALC = “0”)
Manual Mode
Set (SEL2-0 bits or SEL2-0 pins)
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (LMAT, RATT, LMTH)
WR (REF7-0)
WR (IPGA7-0)
(1)
WR (ALC = “1”)
(2)
ALC Operation
No
Finish ALC mode?
(1)
Yes
WR (ALC = “0”)
(2)
Finish ALC mode and return to manual mode
Note : WR : Write
Figure 13. Registers set-up sequence at ALC operation
(1): Enable soft mute (2): Disable soft mute
Note : After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation.
MS0526-E-00
- 27 -
2006/07