AK5366VR Datasheet, PDF (36/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
R/W
Default
D7
IPGL7
IPGR7
R/W
1
D6
IPGL6
IPGR6
R/W
0
D5
IPGL5
IPGR5
R/W
0
D4
IPGL4
IPGR4
R/W
0
D3
IPGL3
IPGR3
R/W
0
D2
IPGL2
IPGR2
R/W
0
D1
IPGL1
IPGR1
R/W
0
D0
IPGL0
IPGR0
R/W
0
IPGL/R7-0: Input PGA & Digital volume control (see Table 17)
Initial values are “80H”.
The data must not be written under 80H.
Writing to the area over 7FH (Table 17) of IPGL/R registers (04H, 05H) is ignored during ALC operation. After
ALC is disabled, the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the
DATT area (Table 11) of DATT registers (08H, 09H), the DATT changes even if ALC is enabled.
Data (hex)
A4H
:
9EH
:
98H
97H
96H
:
82H
81H
80H
Gain (dB) Step width (dB)
+18
0.5
:
0.5
+15
0.5
:
0.5
+12
0.5
IPGA
+11.5
+11
0.5
0.5
Analog volume with 0.5dB step
:
0.5
+1.0
0.5
+0.5
0.5
0
-
Table 17. IPGA Code Table
MS0526-E-00
- 36 -
2006/07