AK5366VR Datasheet, PDF (16/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
OPERATION OVERVIEW
„ System Clock
MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. MCLK frequency is automatically detected in slave mode.
Table 1 shows the relationship of typical sampling frequency and the system clock frequency. Setting of CKS 1-0 bit is
ignored.
MCLK (256fs/384fs/512fs) is required in master mode. MCLK frequency is selected by CKS1-0 bits as shown in Table 2.
In master mode, after setting CKS1-0 bits, there is a possibility the frequency and duty of LRCK and BICK outputs
become an abnormal state.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” and PWN bit = “1”. If these clocks
are not provided, the AK5366VR may draw excess current due to its use of internal dynamically refreshed logic. If the
external clocks are not present, place the AK5366VR in power-down mode (PDN pin = “L” or PWN bit = “0”). In master
mode, the master clock (MCLK) must be provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
MCLK
256fs
384fs
512fs
8.192MHz
12.288MHz
16.384MHz
11.2896MHz
16.9344MHz
22.5792MHz
12.288MHz
18.432MHz
24.576MHz
Table 1. System clock example (Slave mode)
CKS1
CKS0
MCLK
0
0
256fs
Default
0
1
512fs
1
0
384fs
1
1
N/A
Table 2. Master clock frequency select (Master mode)
MS0526-E-00
- 16 -
2006/07