AK5366VR Datasheet, PDF (11/42 Pages) Asahi Kasei Microsystems – 24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC

ASAHI KASEI
[AK5366VR]
SWITCHING CHARACTERISTICS
(Ta=−40 ∼ 85°C; AVDD=4.75 ∼ 5.25V; DVDD, TVDD=3.0 ∼ 5.25V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
8.192
Pulse Width Low
tCLKL 0.3/fCLK
Pulse Width High
tCLKH 0.3/fCLK
AC Pulse Width
(Note 19) tACW 0.4/fCLK
LRCK Frequency
Frequency
fsn
32
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
BICK Period
tBCK
160
BICK Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK Edge to BICK “↑”
(Note 20) tLRB
30
BICK “↑” to LRCK Edge
(Note 20) tBLR
30
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
BICK “↓” to SDTO
tBSD
Master mode
BICK Frequency
fBCK
64fs
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
dBCK
50
tMBLR
−20
tBSD
−20
max
24.576
48
55
Units
MHz
ns
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
35
ns
35
ns
Hz
%
20
ns
35
ns
Note 19. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground.
Note 20. BICK rising edge must not occur at the same time as LRCK edge.
MS0526-E-00
- 11 -
2006/07