3X38FTR Datasheet, PDF (48/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
Register Information (continued)
Table 23. MR1—Status Register Bit Descriptions (continued)
Bit*
Type^†
Description
1.2 (LSTAT_OK)
1.1 (JABBER)
1.0 (EXT_ABLE)
R Link Status. When this bit is a 1, it indicates a valid link has been established.
This bit has a latching function: a link failure will cause the bit to clear and stay
cleared until it has been read via the management interface.
R Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will
remain set until it is read, and the jabber condition no longer exists.
R Extended Capability. This bit indicates that the 3X38 supports the extended
register set (MR2 and beyond). It will always read a 1.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read.
Table 24. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions
Bit*
Type^†
Description
2.15:0 (OUI[3:18]) R Organizationally Unique Identifier. The third through the twenty-fourth bit of the
OUI assigned to the PHY manufacturer by the IEEE are to be placed in bits 2.15:0
and 3.15:10. The value of bits 15:0 is 0180h.
3.15:10 (OUI[19:24]) R Organizationally Unique Identifier. The remaining 6 bits of the OUI. The value
for bits 15:10 is 1Dh.
3.9:4 (MODEL[5:0]) R Model Number. 6-bit model number of the device. The model number is 38h.
3.3:0 (VERSION[3:0]) R Revision Number. The value of the present revision number is 3h.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read.
Table 25. MR4—Autonegotiation Advertisement Register Bit Descriptions
Bit*
Type^†
Description
4.15 (NEXT_PAGE) R/W Next Page. The next page function is activated by setting this bit to a 1. This will
allow the exchange of additional data. Data is carried by optional next pages of
information.
4.14 (ACK)
R/W Acknowledge. This bit is the acknowledge bit from the link code word.
4.13 (REM_FAULT) R/W Remote Fault. When set to 1, the 3X38 indicates to the link partner a remote fault
condition.
4.12:11
(RESERVED)
NA Reserved. These bits will read zero.
4.10 (PAUSE)
R/W Pause. When set to a 1, it indicates that the 3X38 wishes to exchange flow con-
trol information with its link partner.
4.9 (100BASET4) R/W 100Base-T4. This bit should always be set to 0.
4.8 (100BASET_FD) R/W 100Base-TX Full Duplex. If written to 1, autonegotiation will advertise that the
3X38 is capable of 100Base-TX full-duplex operation.
4.7 (100BASETX)
R/W 100Base-TX. If written to 1, autonegotiation will advertise that the 3X38 is capa-
ble of 100Base-TX operation.
4.6 (10BASET_FD) R/W 10Base-T Full Duplex. If written to 1, autonegotiation will advertise that the 3X38
is capable of 10Base-T full-duplex operation.
4.5 (10BASET)
R/W 10Base-T. If written to 1, autonegotiation will advertise that the 3X38 is capable of
10Base-T operation.
4.4:0 (SELECT) R/W Selector Field. Reset with the value 00001 for IEEE 802.3.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write.
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