3X38FTR Datasheet, PDF (43/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Functional Description (continued)
Table 16. Bicolor LED Mode Descriptions
R20B10
1
0
0
0
R20B9
x
1
0
1
R20B8
x
0
1
1
State
Bicolor Mode
Continuously Flash Yellow (320 ms on, 320 ms off)
Continuously Flash Green (320 ms on, 320 ms off)
NA
Reset Operation
The 3X38 can be reset either by hardware or software. A hardware reset is accomplished by applying a negative
pulse, with a duration of at least 1 ms to the RESET_NOT pin of the 3X38 during normal operation. The device
does not internally generate a hardware reset during powerup, an external reset pulse will have to be applied. The
3X38 will come out of RESET after 2 ms. A software reset is activated by setting the reset bit in the basic mode
control register (bit 15, register 00h). This bit is self-clearing and, when set, will return a value of 1 until the software
reset operation has completed.
Hardware reset operation samples the pins and initializes all registers to their default values. This process includes
re-evaluation of all hardware-configurable registers. A hardware reset affects all eight PHYs in the device.
A software reset can reset an individual PHY, and it does not latch the external pins but does reset the registers to
their respective default values.
Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of 3X38.
Some of these pins are used as output ports after reset operation.
Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated con-
figuration pins can be tied to Vcc or ground directly. Configuration pins multiplexed with logic level output functions
should be either weakly pulled up or weakly pulled down through resistors. Configuration pins multiplexed with LED
outputs should be set up with one of the following circuits shown in Figure 15.
VDD
R1
R2
I/O PIN
R2
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
Note: If a resistor value other then 1.5 kΩ is used for the LED current limit resistor the configuration pull-up should also be this value.
5-6783(F).d
Figure 15. Hardware Reset Configuration
Lucent Technologies Inc.
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