3X38FTR Datasheet, PDF (35/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Functional Description (continued)
Data Descrambling
The descrambler acquires synchronization with the
data stream by recognizing IDLE bursts of 40 or more
bits and locking its deciphering linear feedback shift
register (LFSR) to the state of the scrambling LFSR.
Upon achieving synchronization, the incoming data is
XORed by the deciphering LFSR and descrambled.
In order to maintain synchronization, the descrambler
continuously monitors the validity of the unscrambled
data that it generates. To ensure this, a link state moni-
tor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the
descrambler, the hold timer starts a 722 µs countdown.
Upon detection of sufficient IDLE symbols within the
722 µs period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue
indefinitely given a properly operating network connec-
tion with good signal integrity. If the link state monitor
does not recognize sufficient unscrambled IDLE sym-
bols within the 722 µs period, the descrambler will be
forced out of the current state of synchronization and
reset in order to reacquire synchronization.
Symbol Alignment
The symbol alignment circuit in the 3X38 determines
code word alignment by recognizing the /J/K delimiter
pair. This circuit operates on unaligned data from the
descrambler. Once the /J/K symbol pair (11000 10001)
is detected, subsequent data is aligned on a fixed
boundary.
Symbol Decoding
The symbol decoder functions as a look-up table that
translates incoming 5B symbols into 4B nibbles. The
symbol decoder first detects the /J/K symbol pair pre-
ceded by IDLE symbols and replaces the symbol with
MAC preamble. All subsequent 5B symbols are con-
verted to the corresponding 4B nibbles for the duration
of the entire packet. This conversion ceases upon the
detection of the /T/R symbol pair denoting the end-of-
stream delimiter (ESD). The translated data is pre-
sented on the RXD[3:0] signal lines with RXD[0] repre-
senting the least significant bit of the translated nibble.
Valid Data Signal
The valid data signal (RXDV) indicates that recovered
and decoded nibbles are being presented on the
RXD[3:0] outputs synchronous to RXCLK. RXDV is
asserted when the first nibble of translated /J/K is
ready for transfer over the internal MII. It remains active
until either the /T/R delimiter is recognized, link test
indicates failure, or no signal is detected. On any of
these conditions, RXDV is deasserted.
Receiver Errors
The RXER signal is used to communicate receiver
error conditions. While the receiver is in a state of hold-
ing RXDV asserted, the RXER will be asserted for each
code word that does not map to a valid code-group.
100Base-X Link Monitor
The 100Base-X link monitor function allows the
receiver to ensure that reliable data is being received.
Without reliable data reception, the link monitor will halt
both transmit and receive operations until such time
that a valid link is detected.
The 3X38 performs the link integrity test as outlined in
IEEE 100Base-X (Clause 24) link monitor state dia-
gram. The link status is multiplexed with 10 Mbits/s link
status to form the reportable link status bit in serial
management register 1 and driven to the LNKLED
pins.
When persistent signal energy is detected on the net-
work, the logic moves into a link-ready state after
approximately 500 µs and waits for an enable from the
autonegotiation module. When received, the link-up
state is entered and the transmit and receive logic
blocks become active. Should autonegotiation be dis-
abled, the link integrity logic moves immediately to the
link-up state after entering the link-ready state.
Carrier Sense
Carrier sense (CRS) for 100 Mbits/s operation is
asserted upon the detection of two noncontiguous
zeros occurring within any 10-bit boundary of the
receive data stream.
The carrier sense function is independent of symbol
alignment. In default mode, CRS is asserted during
either packet transmission or reception. When
CRS_SEL is pulled high at powerup or reset, or when
register 29, bit 10 is written to a 1, CRS is asserted
only during packet reception. When the IDLE symbol
pair is detected in the receive data stream, CRS is
deasserted. In repeater mode, CRS is only asserted
due to receive activity. CRS is intended to encapsulate
RXDV.
Lucent Technologies Inc.
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