3X38FTR Datasheet, PDF (28/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
Functional Description (continued)
TX 10 Mbits/s Mode
The RMCLK frequency is 10 times the data rate in this
mode; therefore, the value on RTXD[1:0] will be valid
such that RTXD[1:0] may be sampled every tenth
cycle, regardless of the starting cycle within the group.
TX 100 Mbits/s Mode
There will be valid data on RTXD[1:0] for each RMCLK
period when RTXEN is asserted.
Receive Data Path
RXC (at the internal MII) is derived from the incoming
data and, hence, does not maintain a phase relation-
ship with RMCLK. Therefore, an elasticity buffer is
required on the receive path. The 3X38 provides a
32-bit FIFO (default) to synchronize the receive data to
the system clock. The start of packet latency can be
reduced from 16 bits to 8 bits by writing a 1 to register
20, bit 11. CRS_DV is asserted asynchronously. Pre-
amble is output onto the RMII once the internal signal
RRX_DV is asserted (on the rising edge of the
RMCLK). CRS_DV is deasserted asynchronously with
the fall of RRX_DV, but RCRS_DV keeps toggling as
long as data is being flushed out of the elasticity buffer.
The CRS_DV signal behavior can be modified by regis-
ter 20, bit 12. When this bit is set to 0, CRS causes
CRS_DV to be asserted. When this bit is set to a 1,
only RX_DV causes RX_DV to be asserted; this
ensures that false carrier events do not propagate
through the MAC connected to the 3X38.
RX 10 Mbits/s Mode
After the assertion of RCRS_DV, the receive data sig-
nals, RRXD[1:0], will be 00 until the 10Base-T PHY has
recovered the clock and decoded the receive data.
Since RMCLK is 10 times the data rate in this mode,
the value on RRXD[1:0] will be valid such that it can be
sampled every tenth cycle, regardless of the starting
cycle within the group.
RX 100 Mbits/s Mode
After the assertion of RCRS_DV, the receive data sig-
nals, RRXD[1:0] will be 00 until the start-of-stream
(SSD) delimiter has been detected.
Collision Detection
The RMII does not have a collision signal, so all colli-
sions are detected internal to the MAC. This is an AND
function of RTXEN and RCRS derived from RCRS_DV.
RCRS_DV cannot be directly ANDed with RTXEN
because RCRS_DV may toggle at the end of a frame to
provide separation between RCRS and RRXDV.
Receiver Error
The RRX_ER signal is asserted for one or more
RMCLK periods to indicate that an error was detected
within the current receive frame.
RMCLK
RCRS
RRX_DV
RCRS_DV
RRXD[1:0]
00
01
01
CRS
Figure 8. RMII Receive Timing from Internal MII Signals
00
5-7506(F).a
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Lucent Technologies Inc.