3X38FTR Datasheet, PDF (38/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
Functional Description (continued)
Transmit Driver and Receiver: The 3X38 integrates
all the required signal conditioning functions in its
10Base-T block such that external filters are not
required. Only an isolation transformer and impedance
matching resistors are needed for the 10Base-T trans-
mit and receive interface. The internal transmit filtering
ensures that all the harmonics in the transmit signal are
attenuated properly.
Smart Squelch: The smart squelch circuit is responsi-
ble for determining when valid data is present on the
differential receive. The 3X38 implements an intelligent
receive squelch on the TPI± differential inputs to
ensure that impulse noise on the receive inputs will not
be mistaken for a valid signal. The squelch circuitry
employs a combination of amplitude and timing mea-
surements (as specified in the IEEE 802.3 10Base-T
standard) to determine the validity of data on the
twisted-pair inputs.
The signal at the start of the packet is checked by the
analog squelch circuit, and any pulses not exceeding
the squelch level (either positive or negative, depend-
ing upon polarity) will be rejected. Once this first
squelch level is overcome correctly, the opposite
squelch level must then be exceeded within 150 ns.
Finally, the signal must exceed the original squelch
level within an additional 150 ns to ensure that the input
waveform will not be rejected.
Only after all of these conditions have been satisfied
will a control signal be generated to indicate to the
remainder of the circuitry that valid data is present.
Valid data is considered to be present until the squelch
level has not been generated for a time longer than
200 ns, indicating end of packet. Once good data has
been detected, the squelch levels are reduced to mini-
mize the effect of noise, causing premature end-of-
packet detection. The receive squelch threshold level
can be lowered for use in longer cable applications.
This is achieved by setting bit 4 of register 30.
Carrier Sense: Carrier sense (CRS) is asserted due to
receive activity once valid data is detected via the
smart squelch function.
For 10 Mbits/s half-duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 Mbits/s full-duplex operation, the CRS is
asserted only due to receive activity.
In repeater mode, CRS is only asserted due to receive
activity. CRS is deasserted following an end of packet.
Collision Detection: The RMII does not have a colli-
sion pin. Collision is detected internal to the MAC,
which is generated by an AND function of TXEN and
CRS derived from CRS_DV. CRS_DV cannot be
directly ANDed with TXEN because CRS_DV may tog-
gle at the end of a frame to provide separation between
CRS and RXDV. The internal MII will still generate the
COL signal, but this information is not passed to the
MAC via the RMII.
Link Test Function: A link pulse is used to check the
integrity of the connection with the remote end. If valid
link pulses are not received, the link detector disables
the 10Base-T twisted-pair transmitter, receiver, and col-
lision detection functions.
The link pulse generator produces pulses as defined in
the IEEE 802.3 10Base-T standard. Each link pulse is
nominally 100 ns in duration and is transmitted every
16 ms, in the absence of transmit data.
Automatic Link Polarity Detection: The 3X38's
10Base-T transceiver module incorporates an auto-
matic link polarity detection circuit. The inverted polar-
ity is determined when seven consecutive link pulses of
inverted polarity or three consecutive packets are
received with inverted end-of-packet pulses. If the input
polarity is reversed, the error condition will be automat-
ically corrected and reported in bit 6 of register 28.
The automatic link polarity detection function can be
disabled by setting bit 3 of register 30.
Clock Synthesizer
The 3X38 implements a clock synthesizer that gener-
ates all the reference clocks needed from a single
external frequency source. The clock source must be a
CMOS signal at 50 MHz or 125 MHz ± 100 ppm.
Autonegotiation
The autonegotiation function provides a mechanism for
exchanging configuration information between two
ends of a link segment and automatically selecting the
highest-performance mode of operation supported by
both devices. Fast link pulse (FLP) bursts provide the
signaling used to communicate autonegotiation abilities
between two devices at each end of a link segment. For
further detail regarding autonegotiation, refer to Clause
28 of the IEEE 802.3u specification. The 3X38 sup-
ports four different Ethernet protocols, so the inclusion
of autonegotiation ensures that the highest-perfor-
mance protocol will be selected based on the ability of
the link partner.
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Lucent Technologies Inc.