3X38FTR Datasheet, PDF (4/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
Tables (continued)
Table of Contents (continued)
Page
Table 19. PHY Addresses ......................................................................................................................................................................45
Table 20. Output Pins .............................................................................................................................................................................45
Table 21. Summary of Management Registers (MR) .............................................................................................................................46
Table 22. MR0—Control Register Bit Descriptions.................................................................................................................................46
Table 23. MR1—Status Register Bit Descriptions ..................................................................................................................................47
Table 24. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions.....................................................................................48
Table 25. MR4—Autonegotiation Advertisement Register Bit Descriptions ...........................................................................................48
Table 26. MR5—Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................................................49
Table 27. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions.........................................................49
Table 28. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................................................50
Table 29. MR7—Next Page Transmit Register Bit Descriptions .............................................................................................................50
Table 30. MR20—LED and FIFO Configuration .....................................................................................................................................51
Table 31. MR21—RXER Counter ...........................................................................................................................................................51
Table 32. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions...................................................................................52
Table 33. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ............................................................................53
Table 34. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ..............................................................................54
Table 35. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions.......................................................................................55
Table 36. Absolute Maximum Ratings ....................................................................................................................................................56
Table 37. Operating Conditions ..............................................................................................................................................................56
Table 38. dc Characteristics ...................................................................................................................................................................56
Table 39. System Clock (RMII Mode) .....................................................................................................................................................57
Table 40. Management Clock .................................................................................................................................................................57
Table 41. RMII Receive Timing...............................................................................................................................................................58
Table 42. RMII Transmit Timing ..............................................................................................................................................................58
Table 43. Transmit Timing.......................................................................................................................................................................59
Table 44. SMII Timing.............................................................................................................................................................................59
Table 45. Receive Timing .......................................................................................................................................................................60
Table 46. Reset and Configuration Timing .............................................................................................................................................61
Table 47. PMD Characteristics ...............................................................................................................................................................62
Figures
Page
Figure 1. 3X38 Device Overview ..............................................................................................................................................................6
Figure 2. 3X38 Single-Channel Detail Functions .....................................................................................................................................7
Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface ..................................................................................................................8
Figure 4. Typical Single-Channel Fiber-Optic (FX) Interface ....................................................................................................................9
Figure 5. 3X38 Pinout for RMII Mode.....................................................................................................................................................10
Figure 6. 3X38 Pinout for SMII Mode .....................................................................................................................................................11
Figure 7. Functional Description ............................................................................................................................................................27
Figure 8. RMII Receive Timing from Internal MII Signals.......................................................................................................................28
Figure 9. SMII Connection Diagram .......................................................................................................................................................29
Figure 10. Receive Sequence Diagram .................................................................................................................................................29
Figure 11. Transmit Sequence Diagram .................................................................................................................................................30
Figure 12. 100Base-X Data Path ...........................................................................................................................................................32
Figure 13. 10Base-T Module Data Path.................................................................................................................................................37
Figure 14. Timing Diagram.....................................................................................................................................................................42
Figure 15. Hardware Reset Configuration..............................................................................................................................................43
Figure 16. System Clock ........................................................................................................................................................................57
Figure 17. Management Clock ...............................................................................................................................................................57
Figure 18. RMII Receive Timing.............................................................................................................................................................58
Figure 19. RMII Transmit Timing ............................................................................................................................................................58
Figure 20. Transmit Timing .....................................................................................................................................................................59
Figure 21. SMII Timing ...........................................................................................................................................................................59
Figure 22. Receive Timing .....................................................................................................................................................................60
Figure 23. Reset and Configuration Timing............................................................................................................................................61
Figure 24. PMD Characteristics .............................................................................................................................................................62
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