3X38FTR Datasheet, PDF (24/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
Pin Descriptions (continued)
Table 6. LED and Configuration Pins (continued)
Pin
Signal
Type
Description
175
FDUPLED_4/
RMII_MODE
162, LINKLED_[7:0]/
163, BILINKLED[7:0]/
164, FX_MODE_EN[7:0]
165,
166,
168,
169,
170
O Full-Duplex LED[4]. This LED output can operate as the full-duplex
LED indicator, or as a collision LED indicator, or as a serial LED output.
This output is only valid when the link is up. When the link is operating in
full-duplex mode, this LED output is the full-duplex LED (logic high out-
put). When the link is operating in half-duplex mode, this LED output
becomes the collision LED output (logic high output). 10 mA active-high
output.
I RMII Mode. When pulled high through a 10 kΩ resistor at powerup or
reset, this will place the 3X38 in the SMII mode of operation. When
pulled low, the 3X38 will operate in RMII mode. This pin has an internal
50 kΩ pull-down.
O Link LED[7:0]. This pin indicates good link status on port [7:0]. 10 mA
active-high output.
O Bicolor LED[7:0]. When the 3X38 is placed in the bicolor LED mode by
writting a one to bit 10 of register 20. This bit will go high whenever the
link is up and there is no transmit or receive activity. This output works in
conjunction with the activity LED when in bicolor mode. This is a 10 mA
active-high output.
I FX Mode Enable. At powerup or reset, when pulled high through a
10 kΩ resistor, this pin will enable the FX mode (10Base-T and
100Base-TX disabled). When pulled low, it will enable 10Base-T and
100Base-TX modes (100Base-FX mode disabled). These pins are
ORed with register 29, bit 0 [29.0].
These pins have internal 50 kΩ pull-down resistors.
Table 7. Table Test Mode Pins
Pin
186, 187
189, 188
81
Signal
ATBOP
ATBON
PECP
PECN
IDDQ
161
TDI
86
TDO
85
TMS
83
TCLK
84
TRST
Type
Description
O Reserved. Leave these pins unconnected.
O Reserved. Place a 1 kΩ resistor from these pins to ground. These
resistors control the slew rate of the RMII and SMII outputs.
I IDDQ Mode. Reserved for manufacturing test. For normal use, tie
low.
I Test Data Input. Serial data input to the JTAG TAP controller. Sam-
pled on the rising edge of TCK. When not in JTAG mode, tie low.
O Test Data Output. Serial data output from the JTAG TAP controller.
Updated on the falling edge of TCK. When not in use, leave uncon-
nected.
I Test Mode Select. When pulled high through a 10 kΩ resistor, this
pin selects the JTAG test mode. When not in use, tie low.
I Test Clock. JTAG clock input used to synchronize JTAG control and
data tranfers. When unused, tie low.
I Test Reset. Asynchronous active-low reset input to JTAG tap con-
troller. For normal use, tie low.
24
Lucent Technologies Inc.