3X38FTR Datasheet, PDF (44/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
MII Station Management
Basic Operation
The primary function of station management is to transfer control and status information about the 3X38 to a man-
agement entity. This function is accomplished by the MDC clock input, which has a maximum frequency of
12.5 MHz, along with the MDIO signal.
The MII management interface uses MDC and MDIO to physically transport information between the PHY and the
station management entity.
A specific set of registers and their contents (described in Table 18) defines the nature of the information trans-
ferred across the MDIO interface. Frames transmitted on the MII management interface will have the frame struc-
ture shown in Table 17. The order of bit transmission is from left to right. Note that reading and writing the
management register must be completed without interruption. The port addresses are set by the PHYADD pins
(see Table 19 for more detail).
Table 17. MII Management Frame Format
Read/Write
(R/W)
Pre
ST OP PHY_ADD REGAD TA
R
1. . .1 01 10 AAAAA RRRRR Z0
W
1. . .1 01 01 AAAAA RRRRR 10
DATA
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
IDLE
Z
Z
Table 18. MII Management Frames—Field Descriptions
Field
Pre
ST
OP
PHY_ADD
REGAD
TA
DATA
IDLE
Descriptions
Preamble. The 3X38 will accept frames with no preamble. This is indicated by a 1 in register 1, bit
6.
Start of Frame. The start of frame is indicated by a 01 pattern.
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is a 01.
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY.
The first register address bit transmitted and received is the MSB of the address.
Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the 3X38, these bits are driven to 10 by the station. During a read, the MDIO is not driven
during the first bit time and is driven to a 0 by the 3X38 during the second bit time.
Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
being addressed.
IDLE Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will
be disabled, and the PHY’s pull-up resistor will pull the MDIO line to a logic 1.
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