3X38FTR Datasheet, PDF (27/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Functional Description
The 3X38 integrates eight 100Base-X physical sublay-
ers (PHY), 100Base-TX physical medium dependent
(PMD) transceivers, and eight complete 10Base-T
modules into a single chip for both 10 Mbits/s and
100 Mbits/s Ethernet operation. It also supports
100Base-FX operation through external fiber-optic
transceivers. This device provides a reduced media
independent interface (RMII) or serial media indepen-
dant interface (SMII) to communicate between the
physical signaling and the medium access control
(MAC) layers for both 100Base-X and 10Base-T opera-
tions. Additionally, it provides a shared MII port for inter-
facing to repeater devices. The device is capable of
operating in either full-duplex mode or half-duplex
mode in either 10 Mbits/s or 100 Mbits/s operation.
Operational modes can be selected by hardware con-
figuration pins or software settings of management reg-
isters, or can be determined by the on-chip
autonegotiation logic.
The 10Base-T section of the device consists of the
10 Mbits/s transceiver module with filters and a
Manchester ENDEC module.
The 100Base-X section of the device implements the
following functional blocks:
s 100Base-X physical coding sublayer (PCS)
s 100Base-X physical medium attachment (PMA)
s Twisted-pair transceiver (PMD)
The 100Base-X and 10Base-T sections share the fol-
lowing functional blocks:
s Clock synthesizer module (CSM)
s MII registers
s IEEE 802.3U autonegotiation
Additionally, there is an interface module that converts
the internal MII signals of the PHY to RMII signal pins.
Each of these functional blocks is described below.
Reduced Media Independent Interface (RMII)
This interface reduces the interconnect circuits
between a MAC and PHY. In switch applications, this
protocol helps to reduce the pin count on the switch
ASIC significantly. A regular 16-pin MII reduces to a
6-pin (7 with an optional RXER pin) RMII. The intercon-
nect circuits are the following:
1. RMCLK: A 50 MHz clock.
2. RTXEN.
3. RTXD[1:0].
4. RRXD[1:0].
5. RCRS_DV.
6. RRXER: Mandatory for the PHY, but optional for the
switch.
Transmit Data Path
The PHY uses the 50 MHz RMCLK as its reference so
that TXC (at the internal MII) and RMCLK maintain a
phase relationship. This helps to avoid elasticity buffers
on the transmit side. On the rising edge of RMCLK,
2-bit data is provided on the RMII RTXD[1:0] when
RTXEN is high. TXD[1:0] are ignored when RTXEN is
deasserted.
MAC
MII MAC I/F TO RMII MAC I/F
TXEN
TXD[3:0]
TXER
TXCLK
COL
CRS
RXDV
RXD[3:0]
RXER
RXCLK
RMII
RTXEN
RTXD[1:0]
RCRS_DV
RRXD[1:0]
RRXER
RREFCLK
PHY
RMII PHY I/F TO MII PHY I/F
TXEN
TXD[3:0]
TXER
TXCLK
COL
CRS
RXDV
RXD[3:0]
RXER
RXCLK
50 MHz
Lucent Technologies Inc.
Figure 7. Functional Description
5-7505(F).a
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