3X38FTR Datasheet, PDF (47/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Register Information (continued)
Table 22. MR0—Control Register Bit Descriptions (continued)
Bit*
Type^†
Description
0.10 (ISOLATE) R/W Isolate. When this bit is set to a 1, the MII outputs will be brought to the high-
impedance state. The default state is a 0.
0.9 (REDONWAY) R/W Restart Autonegotiation. Normally, the autonegotiation process is started at pow-
erup. The process may be restarted by setting this bit to a 1. The default state is a
0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to a 1. This bit
is self-cleared when autonegotiation restarts.
0.8 (FULL_DUP) R/W Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0, bit 12) is
enabled. The default state is a 0. This bit is ORed with the FULL_DUP pin (W6).
0.7 (COLTST) R/W Collision Test. When this bit is set to a 1, the 3X38 will assert the internal COL
signal in response to RTX_EN. This bit has no external effect on the RMII or SMII
pins.
0.6:0 (RESERVED) NA Reserved. All bits will read 0.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write, NA = not applicable.
Table 23. MR1—Status Register Bit Descriptions
Bit*
Type^†
Description
1.15 (T4ABLE)
1.14 (TXFULDUP)
1.13 (TXHAFDUP)
1.12 (ENFULDUP)
1.11 (ENHAFDUP)
1.10:7 (RESERVED)
1.6 (NO_PA_OK)
1.5 (NWAYDONE)
1.4 (REM_FLT)
1.3 (NWAYABLE)
R 100Base-T4 Ability. This bit will always be a 0.
0: Not able.
1: Able.
R 100Base-TX Full-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
R 100Base-TX Half-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
R 10Base-T Full-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
R 10Base-T Half-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
R Reserved. All bits will read as a 0.
R Suppress Preamble. When this bit is set to a 1, it indicates that the 3X38
accepts management frames with the preamble suppressed.
R Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation
process has been completed. The contents of registers MR4, MR5, MR6, and
MR7 are now valid. The default value is a 0. This bit is reset when autonegotia-
tion is started.
R Remote Fault. When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. The default is a 0.
R Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform
autonegotiation. The value of this bit is always a 1.
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
† R = read, W = write, NA = not applicable.
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