3X38FTR Datasheet, PDF (34/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Preliminary Data Sheet
September 2000
Functional Description (continued)
Table 11. Symbol Code Scrambler (continued)
Symbol
Name
V
V
V
V
V
5B Code
[4:0]
00110
01000
01100
10000
11001
4B Code
[3:0]
Undefined
Undefined
Undefined
Undefined
Undefined
Interpretation
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
For 100Base-TX applications, the scrambler is required
to control the radiated emissions at the media connec-
tor and on the twisted-pair cable.
The 3X38 implements a data scrambler as defined by
the TP-PMD stream cipher function. The scrambler
uses an 11-bit ciphering linear feedback shift register
(LFSR) with the following recursive linear function:
X[n] = X[n – 11] + X[n – 9] (modulo 2)
The output of the LFSR is combined with data from the
encoder via an exclusive-OR logic function. By scram-
bling the data, the total energy launched onto the cable
is randomly distributed over a wide frequency range.
Parallel-to-Serial and NRZ-to-NRZI Conversion
After the transmit data stream is scrambled, data is
loaded into a shift register and clocked out with a
125 MHz clock into a serial bit stream. The serialized
data is further converted from NRZ-to-NRZI format,
which produces a transition on every logic one and no
transition on logic zero.
Collision Detect
During 100 Mbits/s half-duplex operation, collision con-
dition is detected if the transmitter and receiver become
active simultaneously. Collision detection is indicated
by the COL signal of the internal MII. When the FDUP
LED input configuration is pulled low, the FUDUP LED
outputs are redefined to be COL LED outputs. For full-
duplex applications, the COL signal is never asserted.
100Base-X Receiver
The 100Base-X receiver consists of functional blocks
required to recover and condition the 125 Mbits/s
receive data stream. The 3X38 implements the
100Base-X receive state machine diagram as given in
ANSI */IEEE Standard 802.3U, Clause 24. The
125 Mbits/s receive data stream may originate from the
on-chip, twisted-pair transceiver in a 100Base-TX
application. Alternatively, the receive data stream may
be generated by an external optical receiver as in a
100Base-FX application.
The receiver block consists of the following functional
blocks:
s Equalizer
s Clock recovery module
s NRZI/NRZ and serial/parallel decoder
s Descrambler
s Symbol alignment block
s Symbol decoder
s Collision detect block
s Carrier sense block
s Stream decoder block
Clock Recovery
The clock recovery module accepts 125 Mbits/s scram-
bled NRZI data stream from either the on-chip
100Base-TX receiver or from an external 100Base-FX
transceiver. The 3X38 uses an onboard digital phase-
locked loop (PLL) to extract clock information of the
incoming NRZI data, which is then used to retime the
data stream and set data boundaries.
After power-on or reset, the PLL locks to a free-running
25 MHz clock derived from the external clock source.
When initial lock is achieved, the PLL switches to lock
to the data stream, extracts a 125 MHz clock from the
data, and uses it for bit framing of the recovered data.
NRZI-to-NRZ and Serial-to-Parallel Conversion
The recovered data is converted from NRZI to NRZ.
The data is not necessarily aligned to 4B/5B code-
group’s boundary. XORed by the deciphering LFSR
and descrambled.
* ANSI is a registered trademark of the American National Standards
Institute.
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