3X38FTR Datasheet, PDF (31/64 Pages) Agere Systems – OCTAL-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX

Preliminary Data Sheet
September 2000
3X38FTR 208-Pin SQFP
OCTAL-FET for 10Base-T/100Base-TX/FX
Functional Description (continued)
Media Independent Interface (MII)—Internal
The 3X38 implements IEEE 802.3U Clause 22 compli-
ant MII interface which connects to the MII-RMII mod-
ule. This module converts the 4-bit MII receive data to
2-bit RMII receive data. Similarly, it converts the 2-bit
RMII transmit data (received from the MAC) to 4-bit MII
transmit data. The following describes the internal MII
functions.
Transmit Data Interface
Each internal MII transmit data interface comprises
seven signals: TXD[3:0] are the nibble size data path,
TXEN signals the presence of data on TXD, TXER indi-
cates substitution of data with the HALT symbol, and
TXCLK carries the transmit clock that synchronizes all
the transmit signals. TXCLK is usually supplied by the
on-chip clock synthesizer.
Receive Data Interface
Each internal MII receive data interface also comprises
seven signals: RXD[3:0] are the nibble size data path,
RXDV signals the presence of data on RXD, RXER
indicates the validity of data, and RXCLK carries the
receive clock. Depending upon the operation mode,
RXCLK signal is generated by the clock recovery mod-
ule of either the 100Base-X or 10Base-T receiver.
Status Interface
Two internal MII status signals, COL and CRS, are gen-
erated in each of the eight channels to indicate collision
status and carrier sense status. COL is asserted asyn-
chronously whenever the respective channel of 3X38 is
transmitting and receiving at the same time in a half-
duplex operation mode. CRS is asserted asynchro-
nously whenever there is activity on either the transmit-
ter or the receiver. When CRS_SEL is asserted, CRS
is asserted only when there is activity on the receiver.
Operation Modes
Each channel of the 3X38 supports two operation
modes and an isolate mode as described below.
100 Mbits/s Mode. For 100 Mbits/s operation, the
internal MII operates in nibble mode with a clock rate of
25 MHz. In normal operation, the internal MII data at
RXD[7:0] and TXD[7:0] are 4 bits wide.
10 Mbits/s Mode. For 10 Mbits/s nibble mode opera-
tion, the TXCLK and RXCLK operate at 2.5 MHz. The
data paths are 4 bits wide using TXD[7:0] and
RXD[7:0] signal lines.
MII Isolate Mode. The 3X38 implements an MII isolate
mode that is controlled by bit 10 of each one of the four
control registers (register 0h). At reset, 3X38 will initial-
ize this bit to the logic level transition of the ISOLATE
pin. Setting the bit to a 1 will also put the port in MII iso-
late mode.
When in isolate mode, the specified port on the 3X38
does not respond to packet data present at TXD[3:0],
TXEN, and TXER inputs and presents a logic zero on
the TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL,
and CRS outputs. The 3X38 will continue to respond to
all management transactions while the PHY is in iso-
late mode.
Serial Management Interface (SMI)
The serial management interface is used to obtain sta-
tus and to configure the PHY. This mechanism corre-
sponds to the MII specifications for 100Base-X (Clause
22) and supports registers 0 through 6. Additional ven-
dor-specific registers are implemented within the range
of 16 to 31. All the registers are described in the Regis-
ter Information section on page 46.
Management Register Access
The management interface consists of two pins, man-
agement data clock (MDC) and management data
input/output (MDIO). The 3X38 is designed to support
an MDC frequency specified up to 12.5 MHz. The
MDIO line is bidirectional and may be shared by up to
32 devices.
The MDIO pin requires a 1.5 kΩ pull-up resistor which,
during IDLE and turnaround periods, will pull MDIO to a
logic one state. Each MII management data frame is
64 bits long. The first 32 bits are preamble consisting of
32 continuous logic one bits on MDIO and 32 corre-
sponding cycles on MDC. Following preamble is the
start-of-frame field indicated by a <01> pattern. The
next field signals the operation code (OP). <10> indi-
cates read from MII management register operation,
and <01> indicates write to MII management register
operation. The next two fields are PHY device address
and MII management register address. Both of them
are 5 bits wide, and the most significant bit is trans-
ferred first.
During read operation, a 2-bit turnaround (TA) time
spacing between the register address field and data
field is provided for the MDIO to avoid contention. Fol-
lowing the turnaround time, a 16-bit data stream is read
from or written into the MII management registers of
the 3X38.
Lucent Technologies Inc.
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