EVAL-ADUC831QSZ Datasheet, PDF (61/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
(Ports 0 and 2) are dedicated to bus functions during external
program memory fetches. Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the program counter
(PCL) as an address, and then goes into a float state awaiting
the arrival of the code byte from the program memory. During
the time that the low byte of the program counter is valid on P0,
the signal ALE (Address Latch Enable) clocks this byte into an
address latch. Meanwhile, Port 2 (P2) emits the high byte of
the program counter (PCH), then PSEN strobes the EPROM
and the code byte is read into the ADuC831.
ADuC831
P0
ALE
P2
LATCH
SRAM
D0–D7
(DATA)
A0–A7
LATCH
A8–A15
A16–A23
ADuC831
P0
ALE
P2
PSEN
LATCH
EPROM
D0–D7
(INSTRUCTION)
A0–A7
A8–A15
OE
Figure 57. External Program Memory Interface
Note that program memory addresses are always 16 bits wide,
even in cases where the actual amount of program memory used
is less than 64 kBytes. External program execution sacrifices two
of the 8-bit ports (P0 and P2) to the function of addressing the
program memory. While executing from external program memory,
Ports 0 and 2 can be used simultaneously for read/write access
to external data memory, but not for general-purpose I/O.
Though both external program memory and external data memory
are accessed by some of the same pins, the two are completely
independent of each other from a software point of view. For
example, the chip can read/write external data memory while
executing from external program memory.
Figure 58 shows a hardware configuration for accessing up to
64 kBytes of external RAM. This interface is standard to any 8051
compatible MCU.
ADuC831
P0
ALE
P2
RD
WR
LATCH
SRAM
D0–D7
(DATA)
A0–A7
A8–A15
OE
WE
Figure 58. External Data Memory Interface
(64 K Address Space)
If access to more than 64 kBytes of RAM is desired, a feature
unique to the ADuC831 allows addressing up to 16 MBytes
of external RAM simply by adding an additional latch as illustrated
in Figure 59.
RD
OE
WR
WE
Figure 59. External Data Memory Interface
(16 MBytes Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by a pulse of ALE prior to data
being placed on the bus by the ADuC831 (write operation) or
the SRAM (read operation). Port 2 (P2) provides the data
pointer page byte (DPP) to be latched by ALE, followed by the
data pointer high byte (DPH). If no latch is connected to P2,
DPP is ignored by the SRAM, and the 8051 standard of 64 kBytes
external data memory access is maintained.
Power Supplies
The ADuC831’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or ± 10% of
the nominal 5 V level, the chip will function equally well at any
power supply level between 2.7 V and 5.5 V.
Note: Figures 60 and 61 refer to the PQFP package, for the CSP
package connect the extra DV_DD, DG_ND, AV_DD, and AG_ND in the
same manner. Note: for the CSP package, the bottom paddle
should be left unconnected.
Separate analog and digital power supply pins (AV_DD and DV_DD,
respectively) allow AV_DD to be kept relatively free of noisy digital
signals often present on the system DV_DD line. However, though
you can power AV_DD and DV_DD from two separate supplies if
desired, you must ensure that they remain within ± 0.3 V of one
another at all times in order to avoid damaging the chip (as per the
Absolute Maximum Ratings section). Therefore, it is recommended
that unless AV_DD and DV_DD are connected directly together, you
connect back-to-back Schottky diodes between them as shown
in Figure 60.
DIGITAL SUPPLY
10␮F
+
–
0.1␮F
ANALOG SUPPLY
10␮F
+
–
ADuC831
DV_DD
AV_DD
0.1␮F
DGND
AGND
Figure 60. External Dual-Supply Connections
REV. 0
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