EVAL-ADUC831QSZ Datasheet, PDF(49/76 Page) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

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EVAL-ADUC831QSZ Datasheet, PDF (49/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

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ADuC831

SPE = 0 (I2C ENABLE)

HARDWARE I2C

(SLAVE ONLY)

SFR

BITS

50ns GLITCH

REJECTION FILTER

MCO

I2CM

DVDD

(OFF)

SCLOCK

Figure 42. SCLOCK Pin I/O Functional Equivalent

in I 2C Mode

SPE = 1 (SPI ENABLE)

HARDWARE SPI

(MASTER/SLAVE)

DVDD

Q2 (OFF)

SDATA/

MOSI

Q4 (OFF)

Figure 43. SDATA/MOSI Pin I/O Functional Equivalent

in SPI Mode

SPE = 0 (I2C ENABLE)

SFR

BITS

HARDWARE I2C

(SLAVE ONLY)

50ns GLITCH

REJECTION FILTER

MDI

MDO

DVDD

(OFF)

SDATA/

MOSI

MDE

Read-Modify-Write Instructions

Some 8051 instructions that read a port read the latch, and

others read the pin. The instructions that read the latch rather

than the pins are the ones that read a value, possibly change it,

and then rewrite it to the latch. These are called âread-modify-

writeâ instructions. Listed below are the read-modify-write

instructions. When the destination operand is a port, or a port

bit, these instructions read the latch rather than the pin.

ANL

(Logical AND, e.g., ANL P1, A)

ORL

(Logical OR, e.g., ORL P2, A)

XRL

(Logical EX-OR, e.g., XRL P3, A)

JBC

(Jump if Bit = 1 and Clear Bit, e.g., JBC P1.1,

LABEL)

CPL

(Complement Bit, e.g., CPL P3.0)

INC

(Increment, e.g., INC P2)

DEC

(Decrement, e.g., DEC P2)

DJNZ

(Decrement and Jump if Not Zero, e.g.,

DJNZ P3, LABEL)

MOV PX.Y, C* (Move Carry to Bit Y of Port X)

CLR PX.Y* (Clear Bit Y of Port X)

SETB PX.Y* (Set Bit Y of Port X)

The reason that read-modify-write instructions are directed to the

latch rather than the pin is to avoid a possible misinterpretation of

the voltage level of a pin. For example, a port pin might be used to

drive the base of a transistor. When a 1 is written to the bit, the

transistor is turned on. If the CPU then reads the same port bit at

the pin rather than the latch, it will read the base voltage of the

transistor and interpret it as a logic 0. Reading the latch rather than

the pin will return the correct value of 1.

I2CM

Figure 44. SDATA/MOSI Pin I/O Functional Equivalent

in I 2C Mode

MISO is shared with P3.3 and as such has the same configuration

as shown in Figure 40.

*These instructions read the port byte (all 8 bits), modify the addressed bit, and

then write the new byte back to the latch.

REV. 0

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