EVAL-ADUC831QSZ Datasheet, PDF (15/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

External Data Memory (External XRAM)
Just like a standard 8051 compatible core, the ADuC831 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
The ADuC831, however, can access up to 16 MBytes of external
data memory. This is an enhancement of the 64 kBytes external
data memory space available on a standard 8051 compatible core.
The external data memory is discussed in more detail in the
ADuC831 Hardware Design Considerations section.
Internal XRAM
2 kBytes of on-chip data memory exist on the ADuC831. This
memory, although on-chip, is also accessed via the MOVX
instruction. The 2 kBytes of internal XRAM are mapped into
the bottom 2 kBytes of the external address space if the
CFG831 bit is set. Otherwise, access to the external data memory
will occur just like a standard 8051. When using the internal
XRAM, ports 0 and 2 are free to be used as general-purpose I/O.
FFFFFFH
FFFFFFH
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
000000H
CFG831.0 = 0
000800H
0007FFH
000000H
2 kBYTES
ON-CHIP
XRAM
CFG831.0 = 1
Figure 4. Internal and External XRAM
SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC831 via the SFR area is shown in Figure 5.
All registers, except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
62-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
8051-
COMPATIBLE
CORE
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
2304 BYTES
RAM
ADuC831
4-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
8-CHANNEL
12-BIT ADC
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
2 ؋ 12-BIT DACs
SERIAL I/O
WDT
PSM
TIC
Figure 5. Programming Model
Accumulator SFR (ACC)
ACC is the Accumulator register and is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the Accumulator as A.
B SFR (B)
The B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated as a
general-purpose scratchpad register.
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the top of the stack. The SP register is
incremented before data is stored during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier, the ADuC831 offers an extended 11-bit
stack pointer. The three extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.
REV. 0
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