EVAL-ADUC831QSZ Datasheet, PDF (59/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
INTERRUPT SYSTEM
The ADuC831 provides a total of nine interrupt sources with
two priority levels. The control and configuration of the interrupt
system is carried out through three Interrupt-related SFRs.
IE
IP
IEIP2
Interrupt Enable Register
Interrupt Priority Register
Secondary Interrupt Enable Register
IE
SFR Address
Power-On Default Value
Bit Addressable
Interrupt Enable Register
A8H
00H
Yes
Bit
Name
7
EA
6
EADC
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Table XXVIII. IE SFR Bit Designations
Description
Written by User to Enable “1” or Disable “0” All Interrupt Sources
Written by User to Enable “1” or Disable “0” ADC Interrupt
Written by User to Enable “1” or Disable “0” Timer 2 Interrupt
Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt
Written by User to Enable “1” or Disable “0” Timer 1 Interrupt
Written by User to Enable “1” or Disable “0” External Interrupt 1
Written by User to Enable “1” or Disable “0” Timer 0 Interrupt
Written by User to Enable “1” or Disable “0” External Interrupt 0
IP
SFR Address
Power-On Default Value
Bit Addressable
Bit
Name
7
----
6
PADC
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Interrupt Priority Register
B8H
00H
Yes
Table XXIX. IP SFR Bit Designations
Description
Reserved for Future Use
Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low)
Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low)
Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low)
Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low)
Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low)
Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low)
Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low)
IEIP2
SFR Address
Power-On Default Value
Bit Addressable
Bit
Name
7
----
6
PTI
5
PPSM
4
PSI
3
----
2
ETI
1
EPSMI
0
ESI
Secondary Interrupt Enable Register
A9H
A0H
No
Table XXX. IEIP2 SFR Bit Designations
Description
Reserved for Future Use
Priority for Time Interval Interrupt
Priority for Power Supply Monitor Interrupt
Priority for SPI/I²C Interrupt
This Bit Must Contain Zero
Written by User to Enable “1” or Disable “0” Time Interval Counter Interrupt
Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt
Written by User to Enable “1” or Disable “0” SPI/I²C Serial Port Interrupt
REV. 0
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