EVAL-ADUC831QSZ Datasheet, PDF (35/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
PULSEWIDTH MODULATOR (PWM)
The PWM on the ADuC831 is highly flexible PWM offering
programmable resolution and input clock, and can be config-
ured for any one of six different modes of operation. Two of
these modes allow the PWM to be configured as a ⌺-⌬ DAC
with up to 16 bits of resolution. A block diagram of the PWM is
shown in Figure 26.
f_OSC
T0/ EXTERNAL PWM CLOCK
f_OSC /DIVIDE FACTOR/15
f_OSC /DIVIDE FACTOR
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
16-BIT PWM COUNTER
COMPARE
P2.6
P2.7
MODE PWM0H/L PWM1H/L
Figure 26. PWM Block Diagram
The PWM uses five SFRs: the control SFR (PWMCON), and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON (as described below) controls the different modes of
operation of the PWM as well as the PWM clock frequency.
PWM0H/L and PWM1H/L are the data registers that determine
the duty cycles of the PWM outputs. The output pins that the
PWM uses are determined by the CFG831 register and they can
be either P2.6 and P2.7 or P3.4 and P3.3. In this section of the
data sheet, it is assumed that P2.6 and P2.7 are selected as the
PWM outputs.
To use the PWM user software, first write to PWMCON to select
the PWM mode of operation and the PWM input clock. Writing
to PWMCON also resets the PWM counter. In any of the 16-bit
modes of operation (modes 1, 3, 4, 6), user software should
write to the PWM0L or PWM1L SFRs first. This value is written
to a hidden SFR. Writing to the PWM0H or PWM1H SFRs
updates both the PWMxH and the PWMxL SFRs but does not
change the outputs until the end of the PWM cycle in progress.
The values written to these 16-bit registers are then used in the
next PWM cycle.
PWMCON
SFR Address
Power-On Default Value
Bit Addressable
PWM Control SFR
AEH
00H
No
Bit Name
7
SNGL
6
MD2
5
MD1
4
MD0
3
CDIV1
2
CDIV0
1
CSEL1
0
CSEL0
Table X. PWMCON SFR Bit Designations
Description
Turns Off PWM output at P2.6 or P3.4 Leaving Port Pin Free for Digital I/O.
PWM Mode Bits
The MD2/1/0 bits choose the PWM mode as follows:
MD2 MD1 MD0 Mode
0
0
0
Mode 0: PWM Disabled
0
0
1
Mode 1: Single variable resolution PWM on P2.7 or P3.3
0
1
0
Mode 2: Twin 8-bit PWM
0
1
1
Mode 3: Twin 16-bit PWM
1
0
0
Mode 4: Dual NRZ 16-bit Σ-∆ DAC
1
0
1
Mode 5: Dual 8-bit PWM
1
1
0
Mode 6: Dual RZ 16-bit Σ-∆ DAC
1
1
1
Reserved for future use
PWM Clock Divider
Scale the clock source for the PWM counter as shown below:
CDIV1 CDIV0 Description
0
0
PWM Counter = Selected Clock/1
0
1
PWM Counter = Selected Clock/4
1
0
PWM Counter = Selected Clock/16
1
1
PWM Counter = Selected Clock/64
PWM Clock Divider
Select the clock source for the PWM as shown below:
CSEL1 CSEL0 Description
0
0
PWM Clock = f_{OCS/DIVIDE FACTOR} /15 (see CFG831 register)
0
1
PWM Clock = f_{OCS/DIVIDE FACTOR} (see CFG831 register)
1
0
PWM Clock = External input at P3.4/T0
1
1
PWM Clock = f_OSC
REV. 0
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