EVAL-ADUC831QSZ Datasheet, PDF (6/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
SPECIFICATIONS (continued)
Parameter
POWER REQUIREMENTS ^{19, 20}
Power Supply Voltages
AV_DD/DV_DD to AGND
V_DD = 5 V
4.5
5.5
Power Supply Currents Normal Mode
DV_DD Current
6
AV_DD Current
1.7
DV_DD Current
25
21
AV_DD Current
1.7
Power Supply Currents Idle Mode
DV_DD Current
5
AV_DD Current
0.14
DV_DD Current⁴
11
10
AV_DD Current
0.14
Power Supply Currents Power Down Mode
AV_DD Current
3
DV_DD Current
35
25
160
Typical Additional Power Supply Currents
PSM Peripheral
50
ADC
1.5
DAC
150
V_DD = 3 V
2.7
3.3
3
1.7
12
10
1.7
1
0.14
5
4
0.14
2.5
20
12
125
Unit
V min
V max
V min
V max
mA typ
mA max
mA max
mA typ
mA max
mA typ
mA typ
mA max
mA typ
mA typ
␮A typ
␮A max
␮A typ
␮A typ
␮A typ
mA typ
␮A typ
Test Conditions/Comments
AV_DD /DV_DD = 3 V nom
AV_DD /DV_DD = 5 V nom
MCLKIN = 1 MHz
MCLKIN = 1 MHz
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 1 MHz
MCLKIN = 1 MHz
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 2 MHz or 16 MHz
TIMECON.1 = 0
TIMECON.1 = 1
AV_DD = DV_DD = 5 V
NOTES
1_{Temperature Range –40ºC to +125ºC.}
2_{ADC linearity is guaranteed during normal Micro Converter core operation.}
3_{ADC LSB Size = VREF/2}12 _{i.e., for Internal VREF = 2.5 V, 1 LSB = 610 ␮V and for External VREF =1 V, 1 LSB = 244 ␮V.}
4_{These numbers are not production tested but are guaranteed by design and/or characterization data on production release.}
5_{Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.}
6_{Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve}
these specifications.
7_{SNR calculation includes distortion and noise components.}
8_{Channel-to-channel Crosstalk is measured on adjacent channels.}
9_{The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.}
10_{DAC linearity is calculated using:}
Reduced code range of 100 to 4095, 0 to V_REF range.
Reduced code range of 100 to 3945, 0 to V_DD range.
DAC Output Load = 10 kΩ and 100 pF.
11_{DAC differential nonlinearity specified on 0 to VREF and 0 to VDD ranges}
12_{DAC specification for output impedance in the unbuffered case depends on DAC code.}
13_{DAC specifications for ISINK, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC}
in unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
14_{Measured with VREF and CREF pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference will be determined by the value of the}
decoupling capacitor chosen for both the V_REF and C_REF pins.
15_{When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode the V REF and CREF}
pins need to be shorted together for correct operation.
16_{Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.}
17_{Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40ºC, +25ºC, and +125ºC. Typical endurance at}
25ºC is 700,000 cycles.
18_{Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV}
will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section of this data sheet.
19_{Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:}
Normal Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Executing internal software loop.
Idle Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O pins and Port 1 are open circuit, OSC off, TIC off.
20_{DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.}
Specifications subject to change without notice.
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