EVAL-ADUC831QSZ Datasheet, PDF (34/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
3
DAC LOADED WITH 0FFFH
2
To drive significant loads with the DAC outputs, external buff-
ering may be required (even with the internal buffer enabled),
as illustrated in Figure 25. A list of recommended op-amps is in
Table VI.
1
DAC LOADED WITH 0000H
DAC0
ADuC831
DAC1
0
0
5
10
15
SOURCE/SINK CURRENT – mA
Figure 24. Source and Sink Current Capability with
V_REF = V_DD = 3 V
To reduce the effects of the saturation of the output amplifier at
values close to ground and to give reduced offset and gain errors,
the internal buffer can be bypassed. This is done by setting the
DBUF bit in the CFG831 register. This allows a full rail-to-rail
output from the DAC which should then be buffered externally
using a dual supply op-amp in order to get a rail-to-rail output.
This external buffer should be located as near as physically
possible to the DAC output pin on the PCB. Note the unbuffed
mode only works in the 0 to V_REF range.
Figure 25. Buffering the DAC Outputs
The DAC output buffer also features a high-impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high-impedance state (or
“three-state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, then a pull-down resistor must
be added to each DAC output. Assuming this resistor is in place,
the DAC outputs will remain at ground potential whenever the
DAC is disabled.
–34–
REV. 0