EVAL-ADUC831QSZ Datasheet, PDF (45/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
TIME INTERVAL COUNTER (TIC)
TCEN
32kHz INTERNAL R/C OSC.
A time interval counter is provided on-chip for counting longer
intervals than the standard 8051 compatible timers are capable
ITS0, 1
of. The TIC is capable of timeout intervals ranging from 1/128
second to 255 hours. Furthermore, this counter is clocked by
8-BIT
PRESCALER
an internal R/C oscillator rather than the external crystal and
has the ability to remain active in power-down mode and time
long power-down intervals. This has obvious applications for
HUNDREDTHS COUNTER
HTHSEC
remote battery-powered sensors where regular widely spaced
readings are required. The R/C oscillator is accurate to +10% at
25ºC. Note: Instructions to the TIC SFRs are also clocked at
SECOND COUNTER
SEC
INTERVAL
TIMEBASE
SELECTION
MUX
TIEN
32 kHz, sufficient time must be allowed for in user code for
these instructions to execute.
Six SFRs are associated with the time interval counter, TIMECON
MINUTE COUNTER
MIN
being its control register. Depending on the configuration of the
IT0 and IT1 bits in TIMECON, the selected time counter regis-
ter overflow will clock the interval counter. When this counter is
equal to the time interval value loaded in the INTVAL SFR, the
HOUR COUNTER
HOUR
8-BIT
INTERVAL COUNTER
TII bit (TIMECON.2) is set and generates an interrupt if enabled.
If the ADuC831 is in power-down mode, again with TIC inter-
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
COMPARE
COUNT = INTVAL?
rupt enabled, the TII bit will wake up the device and resume
code execution by vectoring directly to the TIC interrupt service
vector address at 0053H. The TIC-related SFRs are described
TIME INTERVAL
INTVAL
below. Note also that the time-base SFRs can be written initially
with the current time, the TIC can then be controlled and
accessed by user software. In effect, this facilitates the imple-
mentation of a real-time clock. A block diagram of the TIC is
Figure 35. TIC, Simplified Block Diagram
shown in Figure 35.
TIMECON
SFR Address
Power-On Default Value
Bit Addressable
TIC Control Register
A1H
00H
No
Table XVI. TIMECON SFR Bit Designations
Bit
Name
Description
7
----
Reserved for Future Use.
6
TFH
Twenty-Four Hour Select Bit.
Set by the user to enable the Hour counter to count from 0 to 23.
Cleared by the user to enable the Hour counter to count from 0 to 255.
5
ITS1
Interval Timebase Selection Bits.
4
ITS0
Written by user to determine the interval counter update rate.
ITS1
ITS0
Interval Timebase
0
0
1/128 Second
0
1
Seconds
1
0
Minutes
1
1
Hours
3
STI
Single Time Interval Bit.
Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit.
Cleared by user to allow the interval counter to be automatically reloaded and start counting
again at each interval timeout.
2
TII
TIC Interrupt Bit.
Set when the 8-bit Interval Counter matches the value in the INTVAL SFR.
Cleared by user software.
1
TIEN
Time Interval Enable Bit.
Set by user to enable the 8-bit time interval counter.
Cleared by user to disable the interval counter.
0
TCEN
Time Clock Enable Bit.
Set by user to enable the time clock to the time interval counters.
Cleared by user to disable the clock to the time interval counters and reset the time interval SFRs
to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR)
can be written while TCEN is low.
REV. 0
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