EVAL-ADUC831QSZ Datasheet, PDF (48/76 Pages) Analog Devices – MicroConverter®, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU

ADuC831
In general-purpose I/O port mode, Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups (Figure 39) and,
in that state, they can be used as inputs. As inputs, Port 2 pins
being pulled externally low will source current because of the
internal pull-up resistors. Port 2 pins with 0s written to them
will drive a logic low output voltage (V_OL) and will be capable of
sinking 1.6 mA.
P2.6 and P2.7 can also be used as PWM outputs. In the case that
they are selected as the PWM outputs via the CFG831 SFR, the
PWM outputs will overwrite anything written to P2.6 or P2.7.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
ADDR
CONTROL
DV_DD DV_DD
DQ
CL Q
LATCH
INTERNAL
PULL-UP*
P2.x
PIN
*SEE FIGURE 39 FOR
DETAILS OF INTERNAL PULL-UP
Figure 38. Port 2 Bit Latch and I/O Buffer
2 CLK
DELAY
DV_DD
Q1
DV_DD
Q2
DV_DD
Q3
Q
FROM
PORT
LATCH
Px.x
Q4
PIN
Figure 39. Internal Pull-Up Configuration
Port 3
Port 3 is a bidirectional port with internal pull-ups directly con-
trolled via the P3 SFR. Port 3 pins that have 1s written to them
are pulled high by the internal pull-ups, and in that state, can be
used as inputs. As inputs, Port 3 pins being pulled externally low
will source current because of the internal pull-ups. Port 3 pins
with 0s written to them will drive a logic low output voltage (V_OL)
and will be capable of sinking 4 mA.
Port 3 pins also have various secondary functions described in
Table XVIII. The alternate functions of Port 3 pins can only be
activated if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Table XVIII. Port 3, Alternate Pin Functions
Pin Alternate Function
P3.0 RxD (UART Input Pin) (or Serial Data I/O in Mode 0)
P3.1 TxD (UART Output Pin)
(or Serial Clock Output in Mode 0)
P3.2 INT0 (External Interrupt 0)
P3.3 INT1 (External Interrupt 1)/PWM 1/MISO
P3.4 T0 (Timer/Counter 0 External Input)
PWM External Clock/PWM 0
P3.5 T1 (Timer/Counter 1 External Input)
P3.6 WR (External Data Memory Write Strobe)
P3.7 RD (External Data Memory Read Strobe)
P3.4 and P2.3 can also be used as PWM outputs. In the case that
they are selected as the PWM outputs via the CFG831 SFR, the
PWM outputs will overwrite anything written to P3.4 or P3.3.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
ALTERNATE
OUTPUT
FUNCTION
DQ
CL Q
LATCH
DV_DD
INTERNAL
PULL-UP*
P3.x
PIN
READ
PIN
ALTERNATE
INPUT
FUNCTION
*SEE FIGURE 39
FOR DETAILS OF
INTERNAL PULL-UP
Figure 40. Port 3 Bit Latch and I/O Buffer
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I²C pins
(SCLOCK and SDATA/MOSI) also feature both input and
output functions. Their equivalent I/O architectures are illus-
trated in Figure 41 and Figure 43, respectively, for SPI
operation and in Figure 42 and Figure 44 for I²C operation.
Notice that in I²C mode (SPE = 0) the strong pull-up FET
(Q1) is disabled, leaving only a weak pull-up (Q2) present. By
contrast, in SPI mode (SPE = 1) the strong pull-up FET (Q1)
is controlled directly by SPI hardware, giving the pin push/pull
capability.
In I²C mode (SPE = 0) two pull-down FETs (Q3 and Q4)
operate in parallel in order to provide an extra 60% or 70% of
current sinking capability. In SPI mode (SPE = 1), however,
only one of the pull-down FETs (Q3) operates on each pin
resulting in sink capabilities identical to that of Port 0 and
Port 2 pins.
On the input path of SCLOCK, notice that a Schmitt trigger
conditions the signal going to the SPI hardware to prevent false
triggers (double triggers) on slow incoming edges. For incoming
signals from the SCLOCK and SDATA pins going to I²C hard-
ware, a filter conditions the signals in order to reject glitches of
up to 50 ns in duration.
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I²C master mode.
Therefore, if you are not using the SPI or I²C functions, you can
use these two pins to give additional high current digital outputs.
SPE = 1 (SPI ENABLE)
DV_DD
HARDWARE SPI
(MASTER/SLAVE)
Q1
SCHMITT
TRIGGER
Q3
Q2 (OFF)
SCLOCK
PIN
Q4 (OFF)
Figure 41. SCLOCK Pin I/O Functional Equivalent
in SPI Mode
–48–
REV. 0