Z86C34 Datasheet, PDF (60/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
EXPANDED REGISTER FILE CONTROL REGISTERS
ZiLOG
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
Figure 37. Stop-Mode Recovery Register
(WRITE ONLY, except Bit D7, which is READ ONLY)
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after RESET
WDT TAP
00
01 _*
10
11
INT RC OSC
3.5 ms
10 ms
14 ms
56 ms
System Clock
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC _*
1 XTAL
Reserved (Must be 0)
Figure 39. Watch-Dog Timer Mode Register
(WRITE ONLY)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 38. Stop-Mode Recovery Register2
60
PRELIMINARY
DS007601-Z8X0499