Z86C34 Datasheet, PDF (42/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
FUNCTIONAL DESCRIPTION (Continued)
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.
WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP mode. Because XTAL
clock is stopped during STOP mode, the on-board RC must
be selected as the clock source to the POR counter. A 1 in-
dicates active during STOP. The default is 1.
ZiLOG
WDTMR Register Accessibility. The WDTMR register is
accessible only during the first 60 internal system clock cy-
cles from the execution of the first instruction after Power-
On Reset, Watch-Dog Reset, or Stop-Mode Recovery. Af-
ter this point, the register cannot be modified by any means,
intentional or otherwise. The WDTMR cannot be read and
is located in bank F of the Expanded Register Group at ad-
dress location 0FH (Figure 30).
Note: If permanent WDT is selected, the WDT runs in all
modes and can not be stopped or disabled if the on board
RC oscillator is selected as the clock source for WDT.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and WDT
counter chain. If the bit is a 1, the internal RC oscillator is
bypassed and the POR and WDT clock source is driven from
the external pin, XTAL1. The default configuration of this
bit is 0 which selects the internal RC oscillator.
Note: The WDT can be permanently enabled (automatically
enabled after RESET) through a mask programming op-
tion. The option is selected by the customer at the time
of ROM code submission. In this mode, WDT is always
activated when the device comes out of RESET. Execu-
tion of the WDT instruction serves to refresh the WDT
time-out period. WDT operation in the HALT and STOP
Modes is controlled by WDTMR programming. If this
mask option is not selected at the time of ROM code sub-
mission, the WDT must be activated by the user through
the WDT instruction and is always disabled by any reset
to the device.
42
PRELIMINARY
DS007601-Z8X0499