Z86C34 Datasheet, PDF (39/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

ZiLOG
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
Figure 26. Stop-Mode Recovery Register
(WRITE ONLY Except Bit D7, Which Is READ ONLY)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic). This bit is reset to D0
= 0 after a Stop-Mode Recovery.
External Clock Divide-by-Two (D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by 2. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1 = 1). Using this bit together with D7 of
PCON further helps lower EMI (that is, D7 (PCON) = 0, D1
(SMR) = 1). The default setting is 0. Maximum external
clock frequency is 4 MHz when SMR BIT D1 = 1 where
SCLK/TCLK = XTAL.
Stop-Mode Recovery Source (D2, D3, and D4). T h e s e
three bits of the SMR specify the wake-up source of the
STOP recovery (Figure 28 and Table 13). When the Stop-
Mode Recovery Sources are selected in this register, then
SMR2 register bits D0,D1 must be set to 0.
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR circuitry.
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 27. Stop-Mode Recovery Register 2
(0F) DH: WRITE ONLY
DS007601-Z8X0499
PRELIMINARY
39