Z86C34 Datasheet, PDF (24/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
PIN FUNCTIONS (Continued)
Port 1 (P17–P10). Port 1 is an 8-bit, bidirectional, CMOS-
compatible port (Figure 13), with multiplexed Address
(A7–A0) and Data (D7–D0) ports. For the ROM device,
these eight I/O lines are programmed as inputs or outputs,
or can be configured under software control as an Ad-
dress/Data port for interfacing external memory. The input
buffers are Schmitt-triggered and byte-programmed as out-
puts and can be globally programmed as either push-pull
or open-drain. Low-EMI output buffers can be globally pro-
grammed by the software.
Note: Port 1 is not available on the devices in the 28-pin pack-
age, and P01M Register must set Bit D4,D3 as 00. Low-
EMI mode is not supported on the emulator for Port1.
PCON register D4 must be 1.
ZiLOG
Port 1 may be placed under handshake control. In this con-
figuration, Port 3, lines P33 and P34 are used as the hand-
shake controls RDY1 and DAV1 (Ready and Data Avail-
able). Memory locations greater than the internal ROM
address are referenced through Port 1, except for Z86C46.
To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If more than 256
external locations are required, Port 0 outputs the additional
lines.
Port 1 can be placed in the high-impedance state along with
Port 0, AS, DS, and R/W, allowing the Z8 to share common
resources in multiprocessor and DMA applications.
8
Port 1
(I/O or AD7–AD0)
Z8
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Open Drain
OE
Out
In
24
Pull-Up
Transistor Enable
(Mask Option)
PAD
1.5
2.3 Hysteresis @ V_CC = 5.0V
R ≈ 500 KΩ
Figure 13. Port 1 Configuration
Auto Latch
(mask option)
PRELIMINARY
DS007601-Z8X0499