Z86C34 Datasheet, PDF (40/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
FUNCTIONAL DESCRIPTION (Continued)
SMR2 D1 D0
00
V_DD
P20
P23
SMR2 D1 D0
11
P20
P27
SMR2 D1 D0
11
ZiLOG
SMR D4 D3 D2
000
V_DD
P30
P31
P32
SMR
D4 D3 D2
00 1
01 0
01 1
SMR D4 D3 D2
10 0
SMR D4 D3 D2
10 1
P20
P33
P27
P23
Stop-Mode Recovery Edge
Select (SMR)
P33 From Pads
SMR D4 D3 D2
11 0
P20
P27
SMR D4 D3 D2
11 1
To POR
RESET
MUX
To P33 Data
Latch and IRQ1
Digital/Analog Mode
Select (P3M)
Figure 28. Stop-Mode Recovery Source
Table 13. Stop-Mode Recovery Source
SMR:432
D4 D3 D2
000
001
010
011
100
101
110
111
Operation
Description of Action
POR and/or external reset recovery
P30 transition
P31 transition (not in Analog Mode)
P32 transition (not in Analog Mode)
P33 transition (not in Analog Mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
wake up is selected, the Stop-Mode Recovery source must
be kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit
position indicates that a high level on any one of the recov-
ery sources wakes the Z8 from STOP mode. A 0 indicates
low-level recovery. The default is 0 on POR (Figure 28).
This bit is used for either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT RESET. A 1 in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Stop-Mode Recovery Delay Select (D5). T h i s b i t , i f
High, enables the T_POR RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is 1. If the fast
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR2 circuitry.
40
PRELIMINARY
DS007601-Z8X0499