Z86C34 Datasheet, PDF (54/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ASCI STATUS REGISTER (STAT)
(%(A)08H: READ/WRITE)
Table 26. ASCI Status Register (STAT)
Bit
7
6
5
4
3
2
1
0
Receive
Transmit
R
Data
Register
Full
Overrun
Error
(OE)
Parity Error
(PE)
Framing
Error
(FE)
Receiver
Data
Register
Empty
Transmitter
(RDRF)
Interrupt
Enable
Reserved
TDRE)
Interrupt
Enable
(RIE)
(TIE)
W
Reset
0
0
0
0
0
0
0
0
BIT 7 is the Receive Data Register Full
RDRF is set to 1 when the receiver transfers a character from
the RSR into an empty Rx FIFO.
Note: If a framing or parity error occurs, RDRF is still set and
the receive data (which generated the error) is still load-
ed into the FIFO.
When there is more than one character in the FIFO, and soft-
ware reads a character, RDRF either remains set or is cleared
and immediately set again. RDRF is cleared to 0 when the
FIFO becomes empty after reading the RDR and during
Power-On Reset.
Bit 6 is the Overrun Error
An overrun occurs if the receive FIFO is still full when the
receiver completes assembly of a character and is ready to
transfer it to the FIFO. If this situation occurs, the overrun
error bit associated with the previous byte in the FIFO is
set. In this case, the latest data byte is not transferred from
the shift register to the FIFO and is lost.
When an overrun occurs, the receiver does not place any
further data in the FIFO until the most recent good byte
received (the byte with the associated overrun error bit set)
moves to the top of the FIFO and sets the Overrun latch,
and software then clears the Overrun latch. Assembly of
bytes continues in the shift register, but this data is ignored
until the byte with the overrun error reaches the top of the
FIFO and the status is cleared. When set, the bit remains
set until it is cleared by writing a 0 to the EFR bit in the
CNTLA register. The bit is also cleared during Power-On
Reset.
Bit 5 is the Parity Error
A parity error is detected when parity generation and check-
ing is enabled by the MOD1 bit in the CNTLA register and
a character has been assembled in which the parity does not
match that specified by the PEO bit in CNTLB.
Note: PE is FIFOed and the error bit is not actually set until the
associated data becomes available for reading in the
RDR.
When set, the bit remains set until it is cleared by writing
a 0 to the EFT bit in the CNTLA register. The bit is cleared
at Power-On Reset.
Bit 4 is the Framing Error
A framing error is detected when the STOP bit of a character
is sampled as a 0 (space). Like PE, FE is FIFOed and the
error bit is not actually set until the associated data becomes
available for reading in the RDR. When set, the bit remains
set until it is cleared by writing a 0 to the EFR bit in the
CNTLA register. The bit is cleared at Power-On Reset.
Bit 3 is the Receiver Interrupt Enable
RIE should be set to a 1 to enable ASCI receive interrupt
requests. An interrupt (IRQ3) is generated when RDRF (bit
7 of the STAT register) is a 1. A receive interrupt is also
generated if this bit is set to a 1, bit 2 of the ASEXT register
(RX interrupt on the START bit) is set to a 1, and a START
bit is detected by the receiver.
54
PRELIMINARY
DS007601-Z8X0499