Z86C34 Datasheet, PDF (35/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

ZiLOG
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
Select
IRQ (D6, D7)
IRQ
IMR
6
Interrupt
Request
Global
Interrupt
Enable
IPR
PRIORITY
LOGIC
Vector Select
Figure 23. Interrupt Block Diagram
Name
IRQ0
IRQ1,
IRQ2
IRQ3
IRQ4
IRQ5
Table 11. Interrupt Types, Sources, and Vectors
Source
DAV0, IRQ0
IRQ1
DAV2, IRQ2, T_IN
UART (ASCI)
T0
T1
Vector
Location
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
Comments
External (P32), Rise Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Rise Fall Edge Triggered
External (P30), Fall Edge Triggered
Internal
Internal
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. An interrupt ma-
chine cycle activates when an interrupt request is granted.
This action disables all subsequent interrupts, saves the Pro-
gram Counter and Status Flags, and then branches to the
program memory vector location reserved for that interrupt.
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte con-
tain the 16-bit address of the interrupt service routine for
that particular interrupt request. To accommodate polled in-
terrupt systems, interrupt inputs are masked and the Inter-
rupt Request register is polled to determine which of the in-
terrupt requests require service.
DS007601-Z8X0499
PRELIMINARY
35