Z86C34 Datasheet, PDF (34/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
FUNCTIONAL DESCRIPTION (Continued)
ZiLOG
OSC
D1 (SMR)
2
D0 (SMR)
Internal Data Bus
Write
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
6-Bit
8-bit
16
÷4
Down
Down
Counter
Counter
IRQ4
Internal
Clock
External Clock
÷2
T_OUT
P36
Clock
Logic
÷4
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
Internal Clock
Gated Clock
Triggered Clock
TIN P31
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Write
Read
Internal Data Bus
Figure 22. Counter/Timer Block Diagram
Interrupts. The Z8 features six different interrupts from six
different sources. These interrupts are maskable, prioritized
(Figure 23) and the six sources are divided as follows: four
sources are claimed by Port 3 lines P33–P30, and two in
counter/timers (Table 11). The Interrupt Mask Register glo-
bally or individually enables or disables the six interrupt re-
quests.
34
PRELIMINARY
DS007601-Z8X0499