Z86C34 Datasheet, PDF (41/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

ZiLOG
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register. Bits D2, D3, and D4 must be 0.
Table 14. Stop-Mode Recovery Source
SMR:10
D1 D0
0
0
0
1
1
0
Operation
Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it reach-
es its terminal count. The WDT is initially enabled by exe-
cuting the WDT instruction and refreshed on subsequent ex-
ecutions of the WDT instruction. The WDT circuit is driven
by an onboard RC oscillator or external oscillator from the
XTAL1 pin. The POR clock source is selected with bit 4 of
the WDT register (Figure 29).
WDT instruction affects the Z (Zero), S (Sign), and V (Over-
flow) flags. The WDTMR must be written to within 64 in-
ternal system clocks. After that, the WDTMR is WRITE-pro-
tected.
Note: WDT time-out while in STOP mode does not reset SMR,
PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers,
but the POR delay counter is still enabled even though
the SMR stop delay is disabled.
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC External Clock
00
3.5 ms
128 TpC
01*
7 ms
256 TpC
10
14 ms
512 TpC
11
56 ms
2048 TpC
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC*
1 XTAL
Reserved (must be 0)
* Default setting after RESET
Figure 29. Watch-Dog Timer Mode Register (WRITE ONLY)
WDT Time Select. (D0,D1). Selects the WDT time period
and is configured as indicated in Table 15.
Table 15. WDT Time Select
Timeout of
D1 D0 Internal RC OSC
00
3.5 ms min
01
10
7 ms min
14 ms min
11
56 ms min
Notes:
SCLK = system bus clock cycle.
The default on RESET is 7 ms.
Values provided are for V_CC = 5.0V.
Timeout of
System Clock
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
DS007601-Z8X0499
PRELIMINARY
41