Z86C34 Datasheet, PDF (43/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

ZiLOG
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
Reset
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
WDT Select
(WDTMR)
CLK Source
Select
(WDTMR)
XTAL
V_DD
V_LV
WDT TAP SELECT
Internal
RC OSC.
5ms POR 5ms 15ms 25ms 100ms
M
U
X
CK
WDT/POR Counter Chain
CLR
2V Operating
+ Voltage Det.
–
WDT
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
Figure 30. Resets and WDT
Internal
RESET
Low Voltage Protection. An onboard Voltage Compara-
tor checks that V_CC is at the required level to ensure correct
operation of the device. RESET is globally driven if V_CC is
below the specified voltage (Low Voltage Protection). The
minimum operating voltage is varying with the temperature
and operating frequency, while the Low Voltage Protection
(V_LV) varies with temperature only.
The Low Voltage Protection trip voltage (V_LV) is less than
3V and more than 1.4V under the following conditions.
Table 16. Maximum (V_LV) Conditions:
Case 1:
Case 2:
T_A = –40ºC, +105ºC, Internal Clock
Frequency equal or less than 4 MHz
T_A = –40ºC, +85ºC, Internal Clock
Frequency equal or less than 6 MHz
Note: The internal clock frequency relationship to the XTAL
clock is dependent on SMR BIT 0 1 setting.
The device functions normally at or above 3.0V under all
conditions. Below 3.0V, the device functions normally until
the Low Voltage Protection trip point (V_LV) is reached, for
the temperatures and operating frequencies in Case 1 and
Case 2, above. The device is guaranteed to function normally
at supply voltages above the Low Voltage Protection trip
point. The actual Low Voltage Protection trip point is a func-
tion of temperature and process parameters (Figure 36).
DS007601-Z8X0499
PRELIMINARY
43