Z86C34 Datasheet, PDF (23/70 Pages) Zilog, Inc. – CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

ZiLOG
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
Port 0 (P00–P07). Port 0 is an 8-bit, bidirectional, CMOS-
compatible port. These eight I/O lines are configured under
software control as a nibble I/O port (P03–P00 input/output
and P07–P04 input/output), or as an address port for inter-
facing external memory. The input buffers are Schmitt-trig-
gered and nibble-programmed as outputs and can be glo-
bally programmed as either push-pull or open-drain. Low-
EMI output buffers can be globally programmed by the soft-
ware. Port 0 is placed under handshake control. In this con-
figuration, Port 3, lines P32 and P35 are used as the hand-
shake control DAV0 and RDY0. Handshake signal direction
is dictated by the I/O direction (input or output) of Port 0
of the upper nibble P04–P07. The lower nibble must indi-
cate the same direction as the upper nibble.
For external memory references, Port 0 provides address
bits A11–A8 (lower nibble) or A15–A8 (lower and upper
nibble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of Port
0 can be programmed independently as I/O while the lower
nibble is used for addressing. If one or both nibbles are re-
quired for I/O operation, they are configured by writing to
the Port 0 mode register.
In ROMless mode, after a hardware RESET, Port 0 is con-
figured as address lines A15–A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
input after RESET.)
Port 0 can be placed in a high-impedance state along with
Port 1, AS, DS and R/W, allowing the Z8 to share common re-
sources in multiprocessor and DMA applications (Figure 12).
4
Port 0
(I/O or A15–A8)
Z8
4
Handshake Controls
DAV0 and RDY0
(P32 and P35)
Open-Drain
OE
Pull-Up
Transistor Enable
(Mask Option)
PAD
Out
1.5
2.3 Hysteresis @ V_CC = 5.0V
In
R ≈ 500KΩ
Auto Latch
(mask option)
Figure 12. Port 0 Configuration
DS007601-Z8X0499
PRELIMINARY
23