XQV100 Datasheet, PDF (9/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

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QPro Virtex 2.5V QML High-Reliability FPGAs
Calculation of T_ioop as a Function of Capacitance
The values for T_ioop were based on the standard capacitive
load (Csl) for each I/O standard as listed in Table 2.
For other capacitive loads, use the formulas below to calcu-
late the corresponding T_ioop:
T_ioop = T_ioopl + T_opadjust + (C_load - C_sl) * fl
Where:
T_opadjust is reported above in the Output Delay
Adjustment section.
C_load is the capacitive load for the design.
Table 2: Constants for Use in Calculation of T_op
Standard
LVTTL slow 2 mA drive
slew rate _{4 mA drive}
C_sl (pF)
35
35
fl (ns/pF)
0.41
0.20
6 mA drive
35
0.100
8 mA drive
35
0.086
12 mA drive 35
0.058
16 mA drive 35
0.050
Table 2: Constants for Use in Calculation of T_op
Standard
LVCMOS2
C_sl (pF)
35
fl (ns/pF)
0.041
PCI 33 MHz 5V
50
0.050
PCI 33 MHZ 3.3V
10
0.050
GTL
0
0.014
GTL+
0
0.017
HSTL Class I
20
0.022
HSTL Class III
20
0.016
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class 1
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
24 mA drive 35
0.048
LVTTL fast 2 mA drive
35
0.41
slew rate _{4 mA drive}
35
0.20
6 mA drive
35
0.13
8 mA drive
35
0.079
12 mA drive 35
0.044
16 mA drive 35
0.043
24 mA drive 35
0.033
Clock Distribution Guidelines and Switching Characteristics
Speed Grade
-4
Symbol
Description
Device
Min
Max
Units
Global Clock Skew
T_GSKEWIOB Global clock skew between IOB flip-flops
XQV100
XQV300
-
0.15
ns
-
0.18
ns
XQV600
-
0.17
ns
XQV1000
-
0.25
ns
T_GPIO
Global clock PAD to output
All
-
0.9
ns
T_GIO
Global clock buffer I input to O output
All
-
0.9
ns
Notes:
1. These clock-distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
DS002 (v1.5) December 5, 2001
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