XQV100 Datasheet, PDF(17/31 Page) Xilinx, Inc

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XQV100 Datasheet, PDF (17/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

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QPro Virtex 2.5V QML High-Reliability FPGAs

QPro Virtex Pinouts

Pinout Tables

See the Xilinx WebLINX web site (http://www.xil-

inx.com/partinfo/databook.htm) for updates or additional

pinout information. For convenience, Table 3, Table 4 and

Table 5 list the locations of special-purpose and power-sup-

ply pins. Pins not listed are user I/Os.

Table 3: Virtex QFP Package Pinout Information

Pin Name

Device

PQ/HQ240

GCK0

All

GCK1

All

GCK2

All

210

GCK3

All

213

All

CCLK

All

179

PROGRAM

All

122

DONE

All

120

INIT

All

123

BUSY/DOUT

All

178

D0/DIN

All

177

All

167

All

163

All

156

All

145

All

138

All

134

All

124

WRITE

All

185

All

184

TDI

All

183

TDO

All

181

TMS

All

TCK

All

239

VCCINT

All

16, 32, 43, 77, 88, 104,

137, 148, 164, 198, 214,

225

VCCO

All

15, 30, 44, 61, 76, 90,

(The VCCO for the PQ/HQ240 package is common to all eight I/O

banks. Different output standards per I/O bank that require different

105, 121, 136, 150, 165,

180, 197, 212, 226, 240

VCCO values cannot be supported.)

DS002 (v1.5) December 5, 2001

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

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