XQV100 Datasheet, PDF (12/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

QPro Virtex 2.5V QML High-Reliability FPGAs
R
CLB SelectRAM Switching Characteristics
Symbol
Description
Sequential Delays
T_SHCKO
Clock CLK to X/Y outputs (WE active)
Shift-Register Mode
T_SHCKO
Clock CLK to X/Y outputs
Setup Times before Clock CLK
T_AS/T_AH
F/G address inputs
T_DS/T_DH
BX/BY data inputs (DIN)
T_WS/T_WH
CE input (WE)
Shift-Register Mode
T_SHDICK
T_SHCECK
Clock CLK
BX/BY data inputs (DIN)
CE input (WS)
T_WPH
Minimum pulse width, High
T_WPL
Minimum pulse width, Low
T_WC
Minimum clock period to meet address write cycle time
Shift-Register Mode
T_SRPH
T_SRPL
Minimum pulse width, High
Minimum pulse width, Low
Speed Grade
-4
Min Max
Units
-
3.0
ns
-
3.0
ns
Setup Time / Hold Time
0.7 / 0 -
ns
0.9 / 0 -
ns
1.0 / 0 -
ns
0.9
-
ns
1.0
-
ns
3.1
-
ns
3.1
-
ns
6.2
-
ns
3.1
-
ns
3.1
-
ns
BLOCKRAM Switching Characteristics
Speed Grade
-4
Symbol
Description
Min Max Units
Sequential Delays
T_BCKO
Clock CLK to DOUT output
Setup Times Before Clock Clk
-
4.1
ns
T_BACK/T_BCKA
T_BDCK/T_BCKD
T_BECK/T_BCKE
T_BRCK/T_BCKR
T_BWCK/T_BCKW
Clock CLK
ADDR inputs
DIN inputs
EN input
RST input
WEN input
1.5 / 0 -
ns
1.5 / 0 -
ns
3.4 / 0 -
ns
3.2 / 0 -
ns
3.0 / 0 -
ns
T_BPWH
Minimum pulse width, High
2.0
-
ns
T_BPWL
Minimum pulse width, Low
2.0
-
ns
T_BCCS
CLKA -> CLKB setup time for different ports
4.0
-
ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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DS002 (v1.5) December 5, 2001
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Preliminary Product Specification