XQV100 Datasheet, PDF (13/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

R
QPro Virtex 2.5V QML High-Reliability FPGAs
TBUF Switching Characteristics
Symbol
Description
Combinatorial Delays
T_IO
T_OFF
T_ON
IN input to OUT output
TRI input to OUT output high-impedance
Tri input to valid data on OUT output
Speed Grade
-4
Min Max
Units
-
0.0
ns
-
0.2
ns
-
0.2
ns
JTAG Test Access Port Switching Characteristics
Symbol
T_TAPTCK
T_TCKTAP
T_TCKTDO
F_TCK
Description
TMS and TDI setup times before TCK
TMS and TDI hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Speed Grade
-4
Min Max
4.0
-
2.0
-
-
11.0
-
33
Units
ns
ns
ns
MHz
Virtex Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Listed below are representative
values for typical pin locations and normal clock loading.
Values are expressed in nanoseconds unless otherwise
noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade
-4
Symbol
Description
Device
Min Max Units
LVTTL Global Clock Input to Output Delay using Output Flip-flop, XQV100
-
3.6
ns
12 mA, Fast Slew Rate, with DLL. For data output with different
XQV300
-
3.6
ns
standards, adjust the delays with the values shown in "IOB Output
Switching Characteristics Standard Adjustments" on page 8.
XQV600
-
3.6
ns
XQV1000
-
3.6
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V_CC threshold with 35 pF external capacitive load. For different loads, see Table 2.
3. DLL output jitter is already included in the timing calculation.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade
-4
Symbol
Description
Device
Min Max Units
LVTTL Global Clock Input to Output Delay using Output Flip-flop, XQV100
-
5.7
ns
12 mA, Fast Slew Rate, without DLL. For data output with different _XQV300
-
5.9
ns
standards, adjust the delays with the values shown in "IOB Output
Switching Characteristics Standard Adjustments" on page 8.
XQV600
-
6.0
ns
XQV1000
-
6.3
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V_CC threshold with 35 pF external capacitive load. For different loads, see Table 2.
DS002 (v1.5) December 5, 2001
www.xilinx.com
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Preliminary Product Specification
1-800-255-7778