XQV100 Datasheet, PDF (19/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

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QPro Virtex 2.5V QML High-Reliability FPGAs
Table 3: Virtex QFP Package Pinout Information (Continued)
Pin Name
V_REF, Bank 7 (V_REF pins are listed incrementally. Connect all pins
listed for both the required device and all smaller devices listed in the
same package.)
Within each bank, if input reference voltage is not required, all V_REF
pins are general I/O.
GND
Device
XQV100
XQV300
XQV600
All
PQ/HQ240
... + 12
... + 5
... + 11
1, 8, 14, 22, 29, 37, 45, 51,
59, 69, 75, 83, 91, 98,
106, 112, 119, 129, 135,
143, 151, 158, 166, 172,
182, 190, 196, 204, 211,
219, 227, 233
Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information
Pin Name
Device
BG256
BG352
GCK0
All
Y11
AE13
GCK1
All
Y10
AF14
GCK2
All
A10
B14
GCK3
All
B10
D14
M0
All
Y1
AD24
M1
All
U3
AB23
M2
All
W2
AC23
CCLK
All
B19
C3
PROGRAM
All
Y20
AC4
DONE
All
W19
AD3
INIT
All
U18
AD2
BUSY/DOUT
All
D18
E4
D0/DIN
All
C19
D3
D1
All
E20
G1
D2
All
G19
J3
D3
All
J19
M3
D4
All
M19
R3
D5
All
P19
U4
D6
All
T20
V3
D7
All
V19
AC3
WRITE
All
A19
D5
CS
All
B18
C4
TDI
All
C17
B3
TDO
All
A20
D4
TMS
All
D3
D23
TCK
All
A1
C24
DXN
All
W3
AD23
BG432
AL16
AK16
A16
D17
AH28
AH29
AJ28
D4
AH3
AH4
AJ2
D3
C2
K4
K2
P4
V4
AB1
AB3
AG4
B4
D5
B3
C4
D29
D28
AH27
BG560/CG560
AL17
AJ17
D17
A17
AJ29
AK30
AN32
C4
AM1
AJ5
AH5
D4
E4
K3
L4
P3
W4
AB5
AC4
AJ4
D6
A2
D5
E6
B33
E29
AK29
DS002 (v1.5) December 5, 2001
www.xilinx.com
19
Preliminary Product Specification
1-800-255-7778