XQV100 Datasheet, PDF (2/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

QPro Virtex 2.5V QML High-Reliability FPGAs
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Table 1: QPro Virtex Field-Programmable Gate Array Family Members
Device System Gates CLB Array Logic Cells
Maximum
Available I/O
XQV100
108,904
20 x 30
2,700
180
XQV300
322,970
32 x 48
6,912
316
XQV600
661,111
48 x 72
15,552
316
XQV1000 1,124,022
64 x 96
27,648
404
Block RAM Bits
40,960
65,536
98,304
131,072
Max Select
RAM Bits
38,400
98,304
221,184
393,216
Virtex Electrical Characteristics
Based on preliminary characterization. Further changes are not expected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
Virtex DC Characteristics
Absolute Maximum Ratings
Symbol
Description
Min/Max Units
V_CCINT
V_CCO
V_REF
V_IN(3)
Supply voltage relative to GND
Supply voltage relative to GND
Input reference Voltage
Input voltage relative to GND
Using V_REF
Internal threshold
–0.5 to 3.0
V
–0.5 to 4.0
V
–0.5 to 3.6
V
–0.5 to 3.6
V
–0.5 to 5.5
V
V_TS
V_CC
T_STG
T_J
Voltage applied to 3-state output
Longest supply voltage rise time from 1V to 2.375V
Storage temperature (ambient)
Junction temperature
Ceramic packages
Plastic packages
–0.5 to 5.5
V
50
ms
–65 to +150 °C
+150
°C
+125
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. For protracted periods (e.g., longer than a day), V_IN should not exceed V_CCO by more that 3.6V.
2
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification