XQV100 Datasheet, PDF (11/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

R
QPro Virtex 2.5V QML High-Reliability FPGAs
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Speed Grade
-4
Symbol
Description
Min
Max
Units
Combinatorial Delays
T_OPX
F operand inputs to X via XOR
T_OPXB
F operand input to XB output
T_OPY
F operand input to Y via XOR
T_OPYB
F operand input to YB output
T_OPCYF
F operand input to COUT output
T_OPGY
G operand inputs to Y via XOR
T_OPGYB
G operand input to YB output
T_OPCYG
G operand input to COUT output
T_BXCY
BX initialization input to COUT
T_CINX
CIN input to X output via XOR
T_CINXB
CIN input to XB
T_CINY
CIN input to Y via XOR
T_CINYB
CIN input to YB
T_BYP
CIN input to COUT output
Multiplier Operation
-
1.0
ns
-
1.4
ns
-
2.0
ns
-
2.0
ns
-
1.5
ns
-
1.2
ns
-
2.1
ns
-
1.6
ns
-
1.1
ns
-
0.6
ns
-
0.1
ns
-
0.6
ns
-
0.6
ns
-
0.2
ns
T_FANDXB
F1/2 operand inputs to XB output via AND
T_FANDYB
F1/2 operand inputs to YB output via AND
T_FANDCY
F1/2 operand inputs to COUT output via AND
T_GANDYB
G1/2 operand inputs to YB output via AND
T_GANDCY
G1/2 operand inputs to COUT output via AND
Setup and Hold Times before/after Clock CLK
-
0.5
ns
-
1.1
ns
-
0.6
ns
-
0.7
ns
-
0.2
ns
Setup Time / Hold Time
T_CCKX/T_CKCX CIN input to FFX
1.3 / 0
-
ns
T_CCKY/T_CKCY CIN input to FFY
1.4 / 0
-
ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if
a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
www.xilinx.com
11
Preliminary Product Specification
1-800-255-7778