XQV100 Datasheet, PDF (14/31 Pages) Xilinx, Inc – QPro Virtex 2.5V QML

QPro Virtex 2.5V QML High-Reliability FPGAs
R
Minimum Clock to Out for Virtex Devices
With DLL
Without DLL
I/O Standard
All Devices
V100
V300
V600
V1000
Units
LVTTL_S2⁽¹⁾
5.2
6.0
6.1
6.1
6.1
ns
LVTTL_S4⁽¹⁾
3.5
4.3
4.4
4.4
4.4
ns
LVTTL_S6⁽¹⁾
2.8
3.6
3.7
3.7
3.7
ns
LVTTL_S8⁽¹⁾
2.2
3.1
3.1
3.2
3.2
ns
LVTTL_S12⁽¹⁾
2.0
2.9
2.9
3.0
3.0
ns
LVTTL_S16⁽¹⁾
1.9
2.8
2.8
2.9
2.9
ns
LVTTL_S24⁽¹⁾
1.8
2.6
2.7
2.7
2.8
ns
LVTTL_F2⁽¹⁾
2.9
3.8
3.8
3.9
3.9
ns
LVTTL_F4⁽¹⁾
1.7
2.6
2.6
2.7
2.7
ns
LVTTL_F6⁽¹⁾
1.2
2.0
2.1
2.1
2.2
ns
LVTTL_F8⁽¹⁾
1.1
1.9
2.0
2.0
2.0
ns
LVTTL_F12⁽¹⁾
1.0
1.8
1.9
1.9
1.9
ns
LVTTL_F16⁽¹⁾
0.9
1.8
1.8
1.8
1.9
ns
LVTTL_F24⁽¹⁾
0.9
1.7
1.8
1.8
1.9
ns
LVCMOS2
1.1
1.9
2.0
2.0
2.1
ns
PCI33_3
1.5
2.4
2.4
2.5
2.5
ns
PCI33_5
1.4
2.2
2.3
2.3
2.4
ns
GTL
1.6
2.5
2.5
2.6
2.6
ns
GTL+
1.7
2.5
2.6
2.6
2.7
ns
HSTL I
1.1
1.9
2.0
2.0
2.0
ns
HSTL III
0.9
1.7
1.8
1.8
1.9
ns
HSTL IV
0.8
1.6
1.7
1.7
1.8
ns
SSTL2 I
0.9
1.7
1.8
1.8
1.8
ns
SSTL2 II
0.8
1.6
1.7
1.7
1.7
ns
SSTL3 I
0.8
1.7
1.7
1.7
1.8
ns
SSTL3 II
0.7
1.5
1.6
1.6
1.7
ns
CTT
1.0
1.8
1.9
1.9
2.0
ns
AGP
1.0
1.8
1.9
1.9
2.0
ns
Notes:
1. S = Slow Slew Rate, F = Fast Slew Rate
2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column. and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
3. Output timing is measured at 50% V_CC threshold with 8 pF external capacitive load.
14
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification